Packet command driving type memory device

A packet command driving type memory device comprising:

• a first signal generating means for receiving a signal being generated from a register and generating a domain signal of certain bit;
• a second and a third signal generating means for generating a first and a second control signal for shifting data;
• a fourth and a fifth signal generating means for generating a third and a fourth control signal for reading data from a core block;
• a data output shift part having a shift means for shifting the data read from the core block according to the first and second control signals generated from the second and the third signal generating means and a clock signal, a data output time compensating means for delaying the data shifted via the shift means by a certain time according to each domain and compensating for a data output time and outputting the compensated signal as read data via a data pad;
• the data output shift part outputs the data transferred via the shift means in a domain 1, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 1t cycle via a delay means and compensating for a data output time in a domain 2, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 2t cycle via a delay means and compensating for a data output time in a domain 3, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 3t cycle via a delay means and compensating for a data output time in a domain 4, outputs the data transferred via the shift means as read data to the data pad directly by delaying them by 4t cycle via a delay means and compensating for a data output time in a domain 5.