Nonvolatile memory structures and fabrication methods

A method for erasing memory cells of a flash memory array formed in and over a semiconductor region, the memory array comprising a plurality of sections each of which can be erased individually, each section having a plurality of memory cells, the method comprising:

• receiving by the memory a command indicating whether the entire memory array is to be erased or less than the entire memory array is to be erased;
• if the entire memory array is to be erased, then erasing the entire memory array in response to the command;
• if less than the entire memory array is to be erased, then erasing a portion of the memory array in response to the command without erasing the entire memory array in response to the command;
• wherein:
• said semiconductor region comprises a continuous first semiconductor region of a first conductivity type, wherein the first semiconductor region comprises channel regions of the memory cells of the array;
• each memory cell of the array further comprises a first source/drain region and a second source/drain region that are regions of a second conductivity type formed in the semiconductor region and adjoining the cell's channel region;
• each memory cell further comprises a conductive floating gate and a conductive control gate;
• if the command indicates that the entire memory array is to be erased, then erasing of the entire array comprises applying a first voltage between the control gate and the channel region of each memory cell of the array, the first voltage being operable to erase the memory cell;
• and
• if the command indicates that less than the entire memory array is to be erased, then erasing said portion of the memory array comprises applying a voltage between the control gate and the first source/drain region of each memory cell of said portion to erase the memory cell while a voltage between the control gate and the channel region of each cell of said portion is lower in magnitude than the first voltage.

A method for accessing a memory comprising a nonvolatile memory array, wherein each memory cell of the array comprises a channel region of a first conductivity type, a first source/drain region of a second conductivity type, and a conductive control gate, the method comprising:

• receiving commands by the memory;
• in response to a first command received by the memory, erasing the entire array, wherein erasing of the array comprises applying a first voltage between the control gate and the channel region of each memory cell of the array, the first voltage being operable to erase each memory cell of the array;
• and
• in response to a second command received by the memory, erasing a portion, but not all, of the array, wherein erasing said portion of the array comprises applying a voltage between the control gate and the first source/drain region of each memory cell of said portion to erase the memory cell while a voltage between the control gate and the channel region of each cell of said portion is lower in magnitude than the first voltage.

An integrated circuit comprising:

• a flash memory array formed in and over a semiconductor region, the memory array comprising a plurality of sections each of which can be erased individually, each section having a plurality of memory cells;
• a first circuit for receiving a command indicating whether the entire memory array is to be erased or less than the entire memory array is to be erased, and for performing the following operations:
• if the entire memory array is to be erased, then erasing the entire memory array in response to the command;
• if less than the entire memory array is to be erased, then erasing a portion of the memory array in response to the command without erasing the entire memory array;
• wherein:
• said semiconductor region comprises a continuous first semiconductor region of a first conductivity type, wherein the first semiconductor region comprises channel regions of the memory cells of the array;
• each memory cell of the array further comprises a first source/drain region and a second source/drain region that are regions of a second conductivity type formed in the semiconductor region and adjoining the cell's channel region;
• each memory cell further comprises a conductive floating gate and a conductive control gate;
• if the command indicates that the entire memory array is to be erased, then erasing of the entire array comprises applying a first voltage between the control gate and the channel region of each memory cell of the array, the first voltage being operable to erase the memory cell;
• and
• if the command indicates that less than the entire memory array is to be erased, then erasing said portion of the memory array comprises applying a voltage between the control gate and the first source/drain region of each memory cell of said portion to erase the memory cell while a voltage between the control gate and the channel region of each cell of said portion is lower in magnitude than the first voltage.

An integrated circuit comprising:

• a flash memory array formed in and over a semiconductor region, the memory array comprising a plurality of sections each of which can be erased individually, each section having a plurality of memory cells;
• a first circuit for receiving a command indicating whether the entire memory array is to be erased or less than the entire memory array is to be erased, and for performing the following operations:
• if the entire memory array is to be erased, then erasing the entire memory array in resopnse to the command;
• if less than the entire memory array is to be erased, then erasing a portion of the memory array in response to the command without erasing the entire memory array;
• each memory cell of the array comprises a conductive floating gate, a conductive control gate, a channel region, and a first source/drain region;
• if the command indicates that the entire memory array is to be erased, then erasing of the entire array comprises applying a first voltage between the control gate and the channel region of each memory cell of the array to induce Fowler-Nordheim tunneling from the floating gate to the channel region to erase the memory cell;
• and
• if the command indicates that less than the entire memory array is to be erased, then erasing said portion of the memory array comprises applying a voltage between the control gate and the first source/drain region of each memory cell of said portion to induce Fowler-Nordheim tunneling from the floating gate to the first source/drain region while a voltage between the control gate and the channel region of each cell of said portion is lower in magnitude than the first voltage.

An integrated circuit comprising:

• a nonvolatile memory array whose memory cells each comprise a channel region of a first conductivity type, a first source/drain region of a second conductivity type, and a conductive control gate;
• wherein the integrated circuit comprises a first circuit for:
• receiving a first command indicating that the entire memory array is to be erased, and erasing the entire array in response to the first command, wherein erasing of the entire array comprises applying a first voltage between the control gate and the channel region of each memory cell of the array, the first voltage being operable to erase the memory cell;
• and
• receiving a second command indicating that less than the entire memory array is to be erased, erasing a portion of the memory array without erasing the entire array in response to the second command, wherein erasing said portion comprises applying a voltage between the control gate and the first source/drain region of each memory cell of said portion to erase the memory cell while a voltage between the control gate and the channel region of each cell of said portion is lower in magnitude than the first voltage.