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AssigneeAdvanced Micro Devices, Inc.
InventorsZhigang Wang, Nian Yang, Jiang Li
Estimating the term…
A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.
In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to said plurality of rows, a plurality of bit lines coupled to said plurality of columns, each of the memory cells comprising a source, a control gate coupled to a word line, and a drain coupled to a bit line, and capable of storing a respective bit, a method for correcting over-erasure of said array of memory cells comprising the step of:
In a non-volatile memory cell comprising a source, a control gate, and a drain, and capable of storing a bit, a method for correcting over-erasure of said non-volatile memory cell comprising the step of:
In a non-volatile memory comprising at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to said plurality of rows, a plurality of bit lines coupled to said plurality of columns, each of the memory cells comprising a source, a control gate coupled to a word line, and a drain coupled to a bit line, and capable of storing a respective bit, a method for correcting over-erasure of said array of memory cells comprising the step of:
Dependencies are inferred from the claim text.