Method of erasing a flash memory
AssigneeSTMicroelectronics S.r.l.
InventorFederico Pio
Life of this patent
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Abstract
A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.
Claims22
A method of erasing a flash memory comprising a semiconductor substrate having at least one well therein, at least one matrix of memory cells in a plurality of rows and a plurality of columns in the at least one well, and a plurality of word lines connected to the memory cells such that each memory cell in a row connects to a corresponding word line, the method comprising:
- applying a single erasing pulse to a selected well and at least one selected word line to thereby erase each memory cell connected thereto and without an intermediate check of completion of erasure;
- the at least one selected word line comprising a selected subset of the plurality of word lines.
A method of erasing a flash memory comprising a semiconductor substrate having at least one well therein, at least one matrix of memory cells in a plurality of rows and a plurality of columns in the at least one well, and a plurality of word lines connected to the memory cells such that each memory cell in a row connects to a corresponding word line, the method comprising:
- applying a single erasing pulse to a selected well and at least one selected word line to thereby erase each memory cell connected thereto and without an intermediate check of completion of erasure;
- the at least one selected word line comprising a selected subset of the plurality of word lines;
- and
- unconditionally programming all erased memory cells to a not-depleted condition by applying a single soft-programming pulse.
A flash memory comprising:
- a semiconductor substrate having at least one well therein;
- at least one matrix of memory cells in a plurality of rows and a plurality of columns in said at least one well;
- and
- a plurality of word lines connected to said memory cells such that each memory cell in a row connects to a corresponding word line;
- each memory cell being erasable with a single erasing pulse applied to a selected well and to at least one selected word line to thereby erase each memory cell connected thereto without an intermediate check of erasure;
- said at least one selected word line comprising a selected subset of the plurality of word lines.
Dependencies are inferred from the claim text.