Channel-erase nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsShigeru Atsumi, Tadayuki Taura, Toru Tanzawa
Life of this patent
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Abstract
In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.
Claims8
A semiconductor memory device comprising:
- a first and a second node which have a potential difference equal to or higher than a supply voltage between them and are connected to each other via a parasitic capacitance;
- a first switch circuit which is connected between said first and second nodes, wherein the first switch circuit short-circuits said first and second nodes, and wherein said first switch circuit includes:
- (a) an n-channel first transistor one end of whose current path is connected to said first node, (b) an n-channel second transistor one end of whose current path is connected to said second node, and (c) a p-channel third transistor both ends of whose current path are connected to the respective other ends of the current paths of said first and second transistors;
- a second switch circuit which is connected between said first node and ground, wherein the second switch circuit is turned on after said first switch circuit has been turned on;
- a third switch circuit which is connected between said second node and ground, wherein the third switch circuit is turned on after said first switch circuit has been turned on;
- and
- a control circuit configured to control said first switch circuit, said control circuit turning on said first switch circuit after an erase operation.
Dependencies are inferred from the claim text.