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US 6,643,181 B2Granted
Method for erasing a memory cell
AssigneeSaifun Semiconductors Ltd.
InventorsYair Sofer, Boaz Eitan
Life of this patent
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Abstract
A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.
Claims26
A method of erasing a bit of a memory cell in a non-volatile memory cell array, the method comprising:
- applying an erase pulse to at least one bit of at least one memory cell of said array;
- erase verifying said at least one bit with a first erase verify level;
- and
- if said bit is erase verified, complete erasing said bit by applying at least one more erase pulse to said at least one bit.
1 more element
A non-volatile memory cell array comprising:
- a plurality of transistor memory cells;
- a power supply adapted to generate erase pulses to bits of said cells;
- and
- a controller in communication with said power supply, said controller adapted to perform the steps of:
- applying an erase pulse to at least one bit of at least one memory cell of said array;
- erase verifying said at least one bit with a first erase verify level;
- and
- if said bit is erase verified, complete erasing said bit by applying at least one more erase pulse to said at least one bit.
5 more elements
Dependencies are inferred from the claim text.