US 6,643,180 B2 · Semiconductor memory device with test mode

Abstract

In a method of testing a nonvolatile semiconductor memory integrated on a semiconductor chip comprising a memory cell array, a first register that stores an address of a defective region in the memory cell array, a plurality of internal voltage generator circuits, and a second register, the second register storing a trimming value for setting an internal voltage value generated by each of the internal voltage generator circuits, the testing method carries out resetting the address of the defective region stored in the first register and the trimming value stored in the second register, and setting the address of the defective region stored in the first register and the trimming value stored in the second register to a value according to a property of each of the semiconductor chips, wherein the testing is carried out without turning a power supply off after the power supply has been turned on.

Claims7

Dependent claims

A semiconductor device comprising:

a bit line;
a plurality of memory cells connected to said bit line;
and
a sense amplifier connected to one end of said bit line;
and
a defect detector circuit configured to detect in a test mode an open-circuit defect or a short-circuit defect of said bit line by reading out data by said sense amplifier while setting all of the plurality of memory cells connected to said bit line to a non-selected state, and connection the other end of said bit line to a predetermined potential via a switch, and judging whether or not data read out by said sense amplifier is a predetermined logic level.

3 more elements

A semiconductor device comprising:

a memory cell array having a column region and a row region in which memory cells are arranged in column and row directions of a matrix;
a redundancy column region having M redundancy columns for replacement with a defective column in said memory cell array;
M registers for storing column addresses to be replaced with said redundancy columns, each of said M registers including a Latch placed to a first or second signal state according to whether or not a corresponding redundancy column can be used;
a sense amplifier;
a counter that selects said M registers sequentially;
a judgment circuit that makes a judgment on whether or not data of a selected column outputted from said sense amplifier coincides with a predetermined expected value and outputs a “pass” or “fail” signal according to a result of said judgment;
and
a control circuit that sets when a defective column in said memory cell array is to be detected in a test mode, a column address and said counter to a start address and thereafter performs following operations until said counter has reached an end column address, increments, if an output of said judgment circuit is “pass”, said column address without registering said column address, stores, if said output of said judgment circuit is “fail” and said latch of said register selected by said counter is set in said first signal state, said column address in said register and thereafter increments said column address and said counter, increments, if said output of said judgment circuit is “fail” and said latch of said resister selected by said counter is placed in said second signal stare, said counter until said counter has reached a register whose latch is placed in said first signal state, thereafter, stores said column address in said register, and thereafter, increments said column address and said counter.

5 more elements

A method of detecting arid replacing a defective column in a semiconductor device in a test mode, said semiconductor device comprising a memory cell array having a column region and a row region in which memory cells are arranged in column and row directions of a matrix;

a redundancy column region having M redundancy columns for replacement with a defective column in said memory cell array;
M registers for storing column addresses to be replaced with said redundancy columns, each of said M registers including a latch placed to a first or second signal state according to whether or not a corresponding redundancy column can be used;
a sense amplifier;
a counter that selects said M registers sequentially;
and a judgment circuit that makes a judgment on whether or not data of a selected column outputted from said sense amplifier coincides with a predetermined expected value and outputs a “pass” or “fail ” signal according to a result of said judgment, wherein,
said method of detecting and replacing a defective column in a semiconductor device in a test mode comprising:
setting a column address and said counter to a starting address, when a defective column in said memory cell array is to be detected;
incrementing, if an output of said judgment circuit is “pass”, said column address without storing said column address, storing, if said output of said judgment circuit is “fail” and said latch of said register selected by said counter is placed in said first signal state, said column address in said register and thereafter incrementing said column address and said counter incrementing, if said output of said judgment circuit is “fail” and said latch of said register selected by said counter is placed in said second signal state, said counter until said counter has reached a register whose lath is placed in said first signal state thereafter, storing said column address in said register and thereafter, incrementing said column address and said counter;
and
carrying out said above operations until said counter has reached and end column address.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with test mode

Life of this patent

Semiconductor memory device with test mode

Life of this patent

Abstract

Claims7