Back to results
US 6,643,175 B2Granted
Nonvolatile semiconductor storage device and test method therefor
AssigneeSharp Kabushiki Kaisha
InventorsYoshimitsu Yamauchi, Nobuhiko Ito
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSharp Kabushiki Kaisha
InventorsYoshimitsu Yamauchi, Nobuhiko Ito
Estimating the term…
A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
A method for testing a nonvolatile semiconductor storage device including floating gate field-effect transistors that are provided with a control gate, a floating gate, a drain and a source, able to electrically write and erase information and arranged in a matrix form on a substrate or a well, including a plurality of row lines connected to the control gates of the floating gate field-effect transistors arranged in a direction of row and including a block switching means for connecting a plurality of first column lines connected to the drains and sources of the floating gate field-effect transistors arranged in a direction of column inside each of blocks constructed by dividing the row lines every several lines to a second column line arranged commonly to all the blocks, the method comprising the steps of:
A method for testing a nonvolatile semiconductor storage device including floating gate field-effect transistors that are provided with a control gate, a floating gate, a drain and a source, able to electrically write and erase information and arranged in a matrix form on a substrate or a well, including a plurality of row lines connected to the control gates of the floating gate field-effect transistors arranged in a direction of row and including a block switching means for connecting a plurality of first column lines connected to the drains and sources of the floating gate field-effect transistors arranged in a direction of column inside each of blocks constructed by dividing the row lines every several lines to a second column line arranged commonly to all the blocks, the method comprising the steps of:
Dependencies are inferred from the claim text.