Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
AssigneeHalo LSI, Inc.
InventorTomoko Ogura
Life of this patent
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Abstract
In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.
Claims20
A bit line decoder circuit for a flash memory array with dual bit cells, comprising:
- a) a flash memory array with a plurality of dual bit memory cells,
- b) a first decoder unit connecting a voltage to bit lines of said memory array,
- c) said bit lines function both as source lines and as drain lines,
- d) a second decoder unit connecting said bit lines to a plurality of intermediate data lines,
- e) a third decoder unit connecting said plurality of intermediate data lines to a plurality of data lines connected to a plurality of sense amplifiers.
A bit line decoder circuit for a dual bit flash memory array, comprising:
- a) a flash memory array with a plurality of dual bit memory cells connected to bit lines, control gate lines and word lines,
- b) said bit lines function both as source lines and as drain lines,
- c) a first decoder unit connecting said bit lines to a plurality of intermediate data lines,
- d) a second decoder unit connecting said plurality of intermediate data lines to a voltage and to a plurality of data lines connected to a plurality of sense amplifiers.
A means for connecting to bit lines of a dual bit flash memory array for read and program operations, comprising:
- a) a means for selecting a plurality of bit lines of a dual bit flash memory array,
- b) a means for connecting a voltage to said plurality of bit lines operating as source lines,
- c) a means for connecting said plurality of bit lines to be read or programmed to a plurality of sense amplifiers.
A method of selecting bit lines of a dual bit flash memory array for read and program operations, comprising:
- a) connecting a voltage to one of a plurality of intermediate data lines,
- b) connecting a plurality of sense amplifiers to said plurality of intermediate data lines,
- c) selecting a plurality of bit lines to be connected to said plurality of intermediate data lines.
Dependencies are inferred from the claim text.