Variable level memory
AssigneeIntel Corporation
InventorsJohn C. Rudelic, Richard E. Fackenthal
Life of this patent
Estimating the term…
Abstract
There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.
Claims56
A method comprising:
- storing data at a first density in a first cell in a first memory array;
- storing data at a second density in a second cell in the first memory array;
- changing the number bits stored per cell on the fly.
An article comprising a medium storing instructions, that, if executed, enable a processor-based system to:
- store data at a first density in a first cell in a first memory array;
- store data at a second density in a second cell in said first memory array;
- and
- change the number of bits stored per cell on the fly.
A memory comprising:
- a memory array including a first and second cell;
- and
- a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell wherein said controller changes the number of bits stored per cell on the fly.
A method comprising:
- storing data at a first density in a first cell in a first memory;
- storing data at a second density in a second cell in the first memory;
- and
- changing a number orbits stored per cell on the fly.
A method comprising:
- storing data at a first density in a first cell in a first memory;
- storing data at a second density in a second cell in the first memory, including storing fewer bits per cell in one of said first or second cells;
- and
- storing data at levels which are spaced from one another in at least one of said first cell and said second cell in order to improve read fidelity.
An article comprising a medium storing instructions that enable a processor-based system to:
- store data at a first density in a first cell in a first memory;
- store data at a second density in a second cell in said first memory;
- and
- store instructions that enable the processor-based system to change a number of bits stored per cell on the fly.
An article comprising a medium storing instructions that enable a processor-based system to:
- store data at a first density in a first cell in a first memory;
- store data at a, second density in a second cell in said first memory;
- and
- store fewer bits per cell in one of said first or second cells;
- and
- store data at levels which are spaced from one another in said cell in order to improve read fidelity.
A memory comprising:
- a memory array including a first and second cell;
- and
- a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell, wherein said controller changes a number of bits stored per cell on the fly.
A memory comprising:
- a memory array including a first and second cell;
- and
- a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell and to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.
A method comprising:
- storing data at a first density in a first cell in a first memory array;
- storing data at a second density in a second cell in the first memory array, so that fewer bits per cell are stored in one of said first and second cells;
- storing data at levels which are spaced from one another in said cells.
An article comprising a medium storing instructions that, if executed, enable a processor-based system to:
- store data at a first density in a first cell in a first memory array;
- store data in a second density in a second cell in said first memory array;
- and
- store data at levels that are spaced from one another in said cell.
A memory comprising:
- a memory array including a first and second cell;
- and
- a controller coupled to said array to store data in said array at a first density in a first cell and to store data at a second density in a second cell, and to store data at levels that are spaced from one another in said cells.
A method comprising:
- storing data at a first density in a first cell in a first memory array;
- storing data at a second density in a second cell in a first memory array;
- and
- storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.
An article comprising a medium storing instructions that, if executed, enable a processor-based system to:
- store data at a first density in a first cell in a first memory array;
- store data at a second density in a second cell in said first memory array;
- and
- store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.
A memory comprising:
- a memory array including a first and second cell;
- and
- a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell and to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.
Dependencies are inferred from the claim text.