Semiconductor memory
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKoji Nii
Life of this patent
Estimating the term…
Abstract
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
Claims3
A semiconductor memory comprising:
- a memory cell having first and second storage terminals storing information of logic levels complementary to each other;
- a power supply wiring supplying a predetermined power supply voltage to said memory cell;
- first and second pairs of bit lines each electrically connected to said first and second storage terminals of said memory cell, when selected;
- and
- first and second word lines connected to said memory cell, said first pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said first word line, and said second pair of bit lines connected to said memory cell and at least reading out data stored at said first and second storage terminals from said memory cell in response to a signal on said second word line, wherein
- said first and second pairs of bit lines and said power supply wiring are provided in parallel to each other, with said power supply wiring interposed between said first and second pairs of bit lines.
Dependencies are inferred from the claim text.