Low power SRAM redundancy repair scheme
AssigneeEtron Technology, Inc.
InventorsTah-Kang Joseph Ting, Bor-Doou Rong, Shi-Huei Liu
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Abstract
A particular SRAM cell power scheme is disclosed. It ensures that overall chip power is reduced, by eliminating power contributed by defective memory array cells. The VSS path to the 6T memory cell is controlled via NMOS transistors. A VSS Enable (VSSEN) circuit is used to decode which block has a defect. Further, the VSSEN signal can be used to selectively disable a defective cell, or block of cells, by cutting the VSS path via turning off the NMOS transistor, in the normal cell region, and the VSSEN signal can be used to selectively enable a redundant cell, or block of cells, by turning on the VSS path via turning on the NMOS transistor, in the redundant cell region.
Claims13
An SRAM memory cell having a redundancy repair scheme, comprising:
- an SRAM memory cell having connections to an upper reference voltage and a lower reference voltage;
- and
- a means for disconnecting said SRAM memory cell from said lower reference voltage wherein said lower reference voltage is always connected to said SRAM memory cell during a test mode and wherein a fuse is blown such that said lower reference voltage is disconnected from said SRAM memory cell.
An SRAM array having a redundancy repair scheme, comprising:
- a plurality of SRAM memory cells having connections to an upper reference voltage and a lower reference voltage, and a means for disconnecting one or more of said SRAM memory cells from said lower reference voltage wherein said lower reference voltage is always connected to said SRAM memory cell during a test mode and wherein a fuse is blown such that said lower reference voltage is disconnected from said SRAM memory cell.
A method to reduce leakage current contributed by defective memory array cells in an SRAM array comprising:
- providing an SRAM array comprising a plurality of SRAM cells (40), each of said cells having a connection to an upper reference voltage and a lower reference voltage;
- testing said SRAM array for defective cells (42);
- replacing said defective cells with redundant good cells (44);
- and
- disconnecting said defective cells from said lower reference voltage (4,6), whereby said leakage current from said defective cells is reduced, while leaving the remaining chip power scheme intact wherein said lower reference voltage is always connected to said cells during a test mode and wherein a fuse is blown such that said lower reference voltage is disconnected from said defective cells.
Dependencies are inferred from the claim text.