Method and circuit for determining sense amplifier sensitivity
AssigneeSTMicroelectronics S.r.l.
InventorDuane Giles Laurent
Life of this patent
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Abstract
A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.
Claims10
A memory device comprising:
- a plurality of bit line pairs, each bit line pair including an even bit line and an odd bit line;
- a plurality of memory cells, each memory cell being coupled to one of the even or the odd bit lines such that each bit line has an equal number of memory cells coupled to it;
- a plurality of sense amplifiers, each sense amplifier coupled to a corresponding one of the bit line pairs;
- an even reference supply line;
- an odd reference supply line;
- for each even bit line, at least one characterization cell coupled between the even reference supply line and the particular even bit line;
- for each odd bit line, at least one characterization cell coupled between the odd reference supply line and the particular odd bit line;
- wherein, at least during a test mode, the even reference supply line is characterized by having a distributed resistance along the even reference supply line.
Dependencies are inferred from the claim text.