Ferroelectric memory having a device responsive to current lowering

A ferroelectric memory comprising:

• a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks;
• a boost power circuit provided in each of said blocks of said memory cell array to generate a boost voltage required for operation of the memory;
• a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each said boost power circuit, and maintaining an ON state during normal operation of the memory;
• a voltage detector circuit for detecting a drop of voltage level of said power line;
• a switch control circuit for turning off said boost power switches in said blocks of said memory cell array excluding the boost power switch in a currently selected block in response to said voltage detector circuit;
• an internal power circuit supplied with the voltage of said power line to output an internal power voltage;
• a first power capacitor connected with said internal power circuit;
• and
• an internal power switch provided between said internal power circuit and said power line to be turned off under control of an output of said voltage detector circuit.