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US 6,643,159 B2Granted
Cubic memory array
AssigneeHewlett-Packard Development Company, L.P.
InventorsPeter Fricke, Andrew L. Van Brocklin, Daryl Anderson
Life of this patent
Estimating the term…
Abstract
A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.
Claims66
A cubic memory array, comprising:
- a substrate having a planar surface;
- a
- a plurality of first select-lines organized in more than one plane parallel to the planar surface;
- a plurality of second select-lines formed in pillars disposed orthogonal to the planer surface of the substrate;
- and
- a plurality of memory cells respectively coupled to the plurality of first and plurality of second select-lines, wherein at least one of the memory cells includes a control element in series with a memory storage element and wherein the memory storage element is formed along the edge of one of the pillars.
3 more elements
An integrated circuit, comprising
- an embedded cubic memory array, the embedded cubic memory array including:
- a substrate having a planar surface;
- a plurality of first select-lines organized in more than one plane parallel to the planar surface;
- a plurality of second select-lines formed in pillars disposed orthogonal to the planer surface of the substrate;
- and
- a plurality of memory cells respectively coupled to the plurality of first and plurality of second select-lines, wherein at least one of the memory cells includes a control element in series with a memory storage element and wherein the memory storage element is formed along the edge of one of the pillars.
3 more elements
A memory carrier, comprising:
- a cubic memory array, including:
- a substrate having a planar surface;
- a plurality of first select-lines organized in more than one plane parallel to the planar surface;
- a plurality of second select-lines formed in pillars disposed orthogonal to the planer surface of the substrate;
- and
- a plurality of memory cells respectively coupled to the plurality of first and plurality of second select-lines, wherein at least one of the memory cells includes a control element in series with a memory storage element and wherein the memory storage element is formed along the edge of one of the pillars.
3 more elements
An electronic device, comprising:
- a cubic memory array, including:
- a substrate having a planar surface;
- a plurality of first select-lines organized in more than one plane parallel to the planar surface;
- a plurality of second select-lines formed in pillars disposed orthogonal to the planer surface of the substrate;
- and
- a plurality of memory cells respectively coupled to the plurality of first and plurality of second select-lines, wherein at least one of the memory cells includes a control element in series with a memory storage element and wherein the memory storage element is formed along the edge of one of the pillars.
3 more elements
A 3D-memory array on a substrate defining a plane, comprising:
- a plurality of memory cells stacked vertically, comprising,
- a dielectric layer forming an insulating surface,
- a first select-line disposed parallel to the plane of the substrate on the dielectric layer,
- a control element surrounding the first select-line, and
- a memory storage element at least partially surrounding the control element;
- and
- a vertical pillar connected to a second select-line, substantially orthogonal to the plane of the substrate and contacting the memory storage element.
4 more elements
A method of creating a memory circuit, comprising the steps of:
- forming an array of first select-lines in a plane substantially parallel to a substrate;
- forming an array of second select-lines normal to plane of the first select-lines;
- and
- forming an array of memory cells, each respectively coupled to a respective first and second select-line, wherein the step of forming an array of memory cells further includes the step of contacting a memory storage device to one of the second select-lines.
1 more element
A method of creating a memory circuit, comprising the steps of:
- forming an array of first select-lines in a plane substantially parallel to a substrate;
- forming an array of second select-lines normal to plane of the first select-lines;
- and
- forming an array of memory cells, each respectively coupled to a respective first and second select-line, wherein the step of forming second select-lines normal to the plane of the first select-lines further includes contacting the memory cells in at least two edges that intersect.
1 more element
A method of fabricating a memory circuit, comprising the steps of:
- applying an insulator on a substrate;
- applying a set of first conductors in one or more planes parallel to the substrate;
- creating a set of control elements on respective first conductors;
- applying a second conductor orthogonal to the planes of the first conductors;
- and
- creating a set of memory storage elements formed along an edge of the second conductor and extending between the second conductor and the respective control elements.
3 more elements
A method of fabricating a memory circuit of N-levels, comprising the steps of:
- (1) applying an insulator on a substrate;
- (2) planarizing the insulator;
- (3) applying a set of first conductors in one or more planes parallel to the substrate;
- (4) creating a set of control elements on respective first conductors;
- (5) applying a second conductor orthogonal to the planes of the first conductors;
- (6) creating a set of memory storage elements formed along an edge of the second conductor and extending between the second conductor and the respective control elements;
- and
- (7) repeating the steps of (1-6) N-times.
5 more elements
A memory circuit, comprising:
- means for selecting a first select-line within an array of memory cells, said means disposed in a plane;
- means for selecting a second select-line within the selected array of memory cells, said means disposed in a direction normal to the plane of said means for selecting a first select-line;
- and
- means for storing a memory state in contact with the means for selecting a second select-line.
1 more element
An integrated circuit, comprising:
- an embedded memory circuit, including:
- means for selecting a first select-line within an array of memory cells, said means disposed in a plane;
- means for selecting a second select-line within the selected array of memory cells, said means disposed in a direction normal to the plane of said means for selecting a first select-line;
- and
- means for storing a memory state in contact with the means for selecting a second select-line.
2 more elements
A memory carrier, comprising:
- a memory circuit, including:
- means for selecting a first select-line within an array of memory cells, said means disposed in a plane;
- means for selecting a second select-line within the selected array of memory cells, said means disposed in a direction normal to the plane of said means for selecting a first select-line;
- and
- means for storing a memory state in contact with the means for selecting a second select-line.
2 more elements
An electronic device, comprising:
- a memory circuit, including:
- means for selecting a first select-line within an array of memory cells, said means disposed in a plane;
- means for selecting a second select-line within the selected array of memory cells, said means disposed in a direction normal to the plane of said means for selecting a first select-line;
- and
- means for storing a memory state in contact with the means for selecting a second select-line.
2 more elements
A computer, comprising:
- at least one memory circuit, including:
- means for selecting a first select-line within an array of memory cells, said means disposed in a plane;
- means for selecting a second select-line within the selected array of memory cells, said means disposed in a direction normal to the plane of said means for selecting a first select-line;
- and
- means for storing a memory state in contact with the means for selecting a second select-line.
2 more elements
A memory cell, comprising:
- a vertical pillar extending from the bottom of the cell to the top of the cell;
- a control element having a first cross sectional area;
- a storage element having a second cross sectional area less than the first cross section area, the storage element in contact with the vertical pillar;
- and
- a middle electrode coupling the control element to the storage element.
2 more elements
Dependencies are inferred from the claim text.