Stress-follower circuit configuration
AssigneeIntel Corporation
InventorMichael J. Allen
Life of this patent
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Abstract
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a stress-follower circuit configuration. The stress-follower circuit of the configuration is coupled to a pad of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in a transistor stack so that in operation the transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack is also coupled to the pad.
Claims13
An integrated circuit comprising:
- a stress-follower circuit configuration;
- the stress-follower circuit configuration being directly connected to a pad of the integrated circuit;
- the stress-follower circuit configuration being coupled so that in operation a transistor in a transistor stack tolerates approximately 1.5 volts above its nominal voltage;
- the transistor stack also being coupled to the pad.
A method of reducing voltage stress on the isolation layer of a transistor coupled to the pad of an integrated circuit including the transistor comprising:
- coupling the isolation layer of the transistor to a voltage bias clamp and coupling another port of the transistor to the pad;
- and
- coupling the voltage bias clamp to the pad via one or more transistors, each of said one or more transistors being structured to tolerate a voltage greater than the nominal transistor operating voltage.
Dependencies are inferred from the claim text.