Multi-processor graphics accelerator
Assignee3Dlabs Inc., Ltd.
InventorsJames L. Deming, Matt E. Buckelew, Clifford A. Whitmore, Steven J. Heinrich, Dale L. Kirkland, Timothy S. Johnson
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Assignee3Dlabs Inc., Ltd.
InventorsJames L. Deming, Matt E. Buckelew, Clifford A. Whitmore, Steven J. Heinrich, Dale L. Kirkland, Timothy S. Johnson
Estimating the term…
An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.
A graphics accelerator for processing a graphics request stream, the accelerator comprising:
A graphics accelerator comprising:
A method for managing the communication, in a graphics accelerator having a plurality of processors coupled to an output bus, of a sequence of data records associated with successive vertices, the plurality of processors being in a peer-to-peer configuration to process the sequence of data records in a cyclical manner, the method comprising:
A method of managing execution of pass-through commands on a graphics accelerator, the graphics accelerator including a plurality of processors that each have inputs for receiving a sequential stream of graphics requests, each processor having an output coupled to a bus, the processors being arranged in a peer-to-peer configuration to process each successive graphics request on a cyclical basis, one of the processors being designated a master processor, the method comprising:
Dependencies are inferred from the claim text.