Method and system for powering down an analog-to-digital converter into a sleep mode
AssigneeCirrus Logic, Inc.
InventorsAryesh Amar, Philip Steiner
Life of this patent
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Abstract
A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.
Claims28
A method for powering down an analog-to-digital converter (“ADC”) into a sleep mode, comprising the steps of:
- in response to an analog-to-digital converter (“ADC”) receiving a normal set of serial clock pulses, outputting, by a serial interface controller, converted data requested by a user through a serial interface;
- in response to the ADC receiving a sleep set of serial clock pulses powering down, by a state machine of the ADC, the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level;
- and
- in response to the ADC being in the sleep mode and the ADC receiving a wake-up set of serial clock pulses, powering up, by the state machine, the ADC from the sleep mode;
- and
- wherein a serial clock signal of the ADC provides either the normal set of serial clock pulses, the sleep set of serial clock pulses or the wake-up set of serial clock pulses and the state machine distinguishes which one of the three sets of serial clock pulses is being provided by the serial clock signal.
A serial interface controller for an analog-to-digital converter (“ADC”) having a digital system and an analog system wherein the serial interface controller allows a serial device to be coupled to the ADC and the serial interface controller controls the ADC in a normal mode or a sleep mode, comprising:
- a state machine having components coupled together in a manner to provide serial interface control operations which include:
- in response to the ADC receiving a normal set of serial clock pulses the serial interface controller outputs converted data requested by a user through a serial interface;
- in response to the ADC receiving a sleep set of serial clock pulses the state machine powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level;
- and
- in response to the ADC being in the sleep mode and the ADC receiving a wake-up set of serial clock pulses, the state machine powers up the ADC from the sleep mode;
- and
- wherein a serial clock signal of the ADC provides either the normal set of serial clock pulses, the sleep set of serial clock pulses, or the wake-up set of serial clock pulses and the state machine distinguishes which one of the three sets of serial clock pulses is being provided by the serial clock signal.
An analog-to-digital converter (“ADC”) for converting analog signals to digital signals, comprising:
- an analog system having a modulator for processing and converting analog signals to digital signals;
- and
- a digital system coupled to the analog system wherein the digital system processes and outputs the digital signals;
- wherein the digital system has a digital logic system, a clock generator, a filter, and a serial port block coupled to each other wherein the serial port block further comprises a serial data interface with a serial interface controller which allows a serial device to be coupled to the ADC and the serial interface controller controls the ADC in a normal mode or a sleep mode, and
- wherein the serial interface controller comprises a state machine having components coupled together in a manner to provide serial interface control operations which include:
- in response to the ADC receiving a normal set of serial clock pulses, the serial interface controller outputs converted data requested by a user through a serial interface;
- in response to the ADC receiving a sleep set of serial clock pulses, the state machine powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level;
- and
- in response to the ADC being in the sleep mode and the ADC receiving a wake-up set of serial clock pulses, the state machine powers up the ADC from the sleep mode;
- and
- wherein a serial clock signal of the ADC provides either the normal set of serial clock pulses, the sleep set of serial clock pulses, or the wake-us set of serial clock pulses and the state machine distinguishes which one of the three sets of serial clock pulses is being provided by the serial clock signal.
A method of utilizing a serial clock signal for controlling an analog-to-digital converter between a normal operational mode and a sleep mode, comprising the steps of:
- sending a sleep clock signal to indicate an analog-to-digital converter (“ADC”) to power down into a sleep mode;
- when the ADC is in the sleep mode, sending a wake up signal to indicate the ADC to power up from the sleep mode;
- and
- sending a normal clock signal to indicate the ADC to convert and output data in a normal operational mode;
- and
- wherein a serial clock signal provides either the sleep clock signal, the wake up signal, or the normal clock signal.
Dependencies are inferred from the claim text.