Apparatus and method for the correction of DC offset in data bus structures at the receiver

A direct current (DC) offset compensation circuit for mitigating DC offset within a plural level received signal transmitted over a pair of differential lines of a parallel interface, the compensation circuit comprising:

• a summer to subtract, from a received signal carried on the pair of differential signal lines, a DC compensation signal;
• integration circuitry to receive and to integrate a compensated training signal and produce an integration value;
• a received signal comparator for signalling when the received signal makes a transition;
• a signal transition smoothing circuit to smooth an output of the integration circuitry;
• an integration value comparator to signal when an integration value provided by the integration circuitry changes in relation to a reference voltage;
• a DC compensation signal adjustment device to output a DC compensation signal and to increase and decrease the DC compensation signal in accordance with when the integration value produced by the integration circuitry is above or below the reference voltage.