Oscillator using virtual stages for multi-gigabit clock recovery
Assignee3Com Corporation
InventorsAnthony Eugene Zortea, Todd Wey
Life of this patent
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Abstract
In a high speed digital communication receiver, an n-stage oscillator of frequency f has a plurality of n stages with n variable analog delays connected to respective ones of the n stages, outputs of the n variable analog delays providing n successive cycles of a clock signal of frequency n×f. A delay control circuit varies the delay interposed by each of the variable delays through a range of 1/(n×f). The delay control circuit can vary the delay in m equal steps, whereby the oscillator exhibits n×m virtual oscillator stages, so that the oscillator provides a phase resolution of 1/(m×n×f).
Claims14
A high-speed clock generator for digital communication systems, comprising:
- a ring oscillator having n stages and n×m virtual stages, said virtual stages comprising n variable analog delays connected to corresponding ones of said n stages and having a delay that is variable over m equal steps within a delay range corresponding to a phase difference between adjacent ones of the n stages;
- a delay control circuit for selecting a delay value for the variable analog delays;
- and
- a comparator having a pair of inputs connected, respectively, to an output of one of said variable analog delays and to one of said n stages, said comparator further having an output connected to said delay control circuit, whereby said delay control circuit causes the delay value of said variable delays to cycle within said delay range.
A high-speed digital communication receiver comprising:
- an oscillator of frequency f having a plurality of n stages connected serially having a delay of 1/(n×f) between successive stages;
- a plurality of n variable analog delays connected to respective ones of said n stages, outputs of said n variable analog delays providing n successive cycles of a clock signal of frequency n×f;
- a delay control circuit varying the delay interposed by each of said variable delays through a range of 1/(n×f);
- and
- a differential phase comparator having a pair of comparator inputs and an output connected to said delay control circuit, one of the comparator inputs being connected to an output of a selected one of said variable analog delays and the other of said comparator inputs being connected to one of the stages.
A ring oscillator having n stages and n×m virtual stages, said virtual stages comprising n variable analog delays connected to corresponding ones of said n stages and having a delay that is variable over m equal steps within a delay range corresponding to a phase difference between adjacent ones of the n stages.
Dependencies are inferred from the claim text.