Self-biased amplifier circuit and method for self-basing amplifier circuit

An amplifier circuit comprising:

• a first input device coupled to a first input node, said first input device controlling a first current flowing from the a supply voltage through a first node to a summing node;
• a second input device coupled to a second input node, said second input device controlling a second current flowing from the first supply voltage through a second node to the summing node;
• a current source device coupled to a bias node, said current source device controlling a summed current flowing from the summing node to the second supply voltage;
• a first current mirror circuit coupled between the first supply voltage and the first node and to an output node, said first current mirror circuit generating a load current mirroring the first current to provide an output signal voltage to said output node, said output node also coupled to said second input node;
• a second current mirror circuit coupled between the first supply voltage and a third node and to the second node, said second current mirror circuit providing a mirrored second current to the third node;
• a third current mirror circuit coupled between the third node and the second supply voltage and to said bias node, said third current mirror circuit pulling a mirrored second current from the bias node;
• a fourth current mirror circuit coupled between the first supply voltage and the first node and to the bias node, said fourth current mirror circuit supplying a mirrored first current to the bias node;
• and
• a capacitor coupled between the bias node and the second supply voltage, said capacitor providing a bias voltage to said current source device.

An amplifier circuit comprising:

• a first transistor of a first conductivity type, a gate of the first transistor being coupled to a first input node, a drain of the first transistor being coupled to the first node, and a source of the first transistor being coupled to the summing node;
• a second transistor of the first conductivity type, a gate of the second transistor being coupled to a second input node, a drain of the second transistor being coupled to the second node, and a source of the second transistor being coupled to the summing node;
• a current source transistor of the first conductivity type, a gate of the current source transistor being coupled to the bias node, a drain of the current source transistor being coupled to the summing node, and a source of the current source transistor being coupled to the second supply voltage;
• a third transistor of a second conductivity type, a gate and a drain of the third transistor being coupled to the first node, and a source of the third transistor being coupled to the first supply voltage;
• and
• a fourth transistor of the second conductivity type, a gate of the fourth transistor being coupled to the first node, a source of the fourth transistor being couple to the first supply voltage, and a drain of the fourth transistor being coupled to an output node, the output node also coupled to the second input node;
• a fifth transistor of the second conductivity type, a gate and a drain of the fifth transistor being coupled to the second node, and a source of the fifth transistor being coupled to the first supply voltage;
• a sixth metal oxide semiconductor field effect transistor of the second conductivity type, a gate of the sixth transistor being coupled to the gate of the fifth transistor, a source of the sixth transistor being couple to the first supply voltage, and a drain of the sixth transistor being coupled to the third node;
• a seventh transistor of the first conductivity type, a gate and a drain of the seventh transistor being coupled to the third node, and a source of the seventh transistor being coupled to the second supply voltage;
• an eighth transistor of the first conductivity type, a gate of the eighth transistor being coupled to the gate of the seventh transistor, a drain of the eighth transistor being coupled to the bias node, and a source of the eighth transistor being couple to the second supply voltage;
• a ninth transistor of the second conductivity type, a gate of the ninth transistor being coupled to the gate of the third transistor, a source of the ninth transistor being couple to the first supply voltage, and a drain of the ninth transistor being coupled to the bias node;
• and
• a capacitor coupled between the bias node and the second supply voltage, said capacitor providing the bias voltage to said current source device.

A method for self-biasing an amplifier circuit including a first input node, a second input node, and an output node, said method comprising:

• receiving an input signal voltage at the first input node;
• controlling a first current flowing from a first supply voltage to a summing node in accordance with the input signal voltage at the first input node;
• generating a load current by mirroring the first current and supplying the load current to the output node to provide an output signal voltage to the output node;
• feeding back the output signal voltage to the second input node;
• controlling a second current flowing from the first supply voltage to the summing node in accordance with the output signal voltage at the second input node;
• generating a mirrored first current by mirroring the first current;
• generating a mirrored second current by mirroring the second current;
• supplying a difference of the mirrored first current and the mirrored second current to a capacitor coupled to a second supply voltage, the capacitor providing a bias voltage in accordance with an electric charge held therein;
• and
• controlling a summed current flowing from the summing node to the second supply voltage in accordance with the bias voltage.