Integrated XOR/summer/multiplexer for high speed phase detection
AssigneeApplied Micro Circuits Corporation
InventorKenneth Smetana
Life of this patent
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Abstract
A high speed phase detector utilizes an integrated XOR/SUMMER/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/SUMMER/MUX circuit combines the functionality of two parallel XOR devices in series with a summer/multiplexer in a manner that reduces the number of gate delays associated with the input signals. In a practical implementation, the XOR/SUMMER/MUX circuit includes XOR arrangements having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/SUMMER/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.
Claims18
An integrated XOR/SUMMER/MUX device comprising:
- a reference voltage node;
- an output voltage node;
- a first XOR arrangement comprising a first collector node corresponding to said reference voltage node, a second collector node corresponding to said output voltage node, and a first common emitter node;
- a second XOR arrangement comprising a third collector node corresponding to said reference voltage node, a fourth collector node corresponding to said output voltage node, and a second common emitter node;
- a differential transistor pair comprising one transistor having a collector connected to said reference voltage node, another transistor having a collector connected to said output voltage node, and a third common emitter node;
- and
- a MUX arrangement comprising a fifth collector node corresponding to said first common emitter node, a sixth collector node corresponding to said second common emitter node, and a seventh collector node corresponding to said third common emitter node.
An integrated XOR/SUMMER/MUX device comprising:
- a reference voltage node;
- an output voltage node;
- a first XOR arrangement coupled to said reference voltage node and to said output voltage node, said first XOR arrangement being configured to perform an XOR operation based upon a first input signal and a second input signal;
- a second XOR arrangement coupled to said reference voltage node and to said output voltage node, said second XOR arrangement being configured to perform an XOR operation based upon a third input signal and a fourth input signal;
- an input arrangement coupled to said reference voltage node and to said output voltage node, said input arrangement being configured to receive a fifth input signal;
- and
- a MUX arrangement coupled to said first XOR arrangement, to said second XOR arrangement, and to said input arrangement, said MUX arrangement being configured to select either said input arrangement or said first and second XOR arrangements for operation in response to a select signal.
An integrated XOR/SUMMER/MUX device comprising:
- an output node configured to provide an output signal;
- a first XOR arrangement coupled to said output node, said first XOR arrangement comprising at least one transistor implemented at a first relative transistor level and at least one transistor implemented at a second relative transistor level, said first XOR arrangement being configured to receive a first input signal and a second input signal and to influence a summed XOR output voltage based upon said first and second input signals;
- a second XOR arrangement coupled to said output node, said second XOR arrangement comprising at least one transistor implemented at said first relative transistor level and at least one transistor implemented at said second relative transistor level, said second XOR arrangement being configured to receive a third input signal and a fourth input signal and to influence said summed XOR output voltage based upon said third and fourth input signals;
- and
- a MUX arrangement coupled to said first and second XOR arrangements, said MUX arrangement comprising at least one transistor implemented at a third relative transistor level, said MUX arrangement being configured to receive a select signal;
- wherein
- in response to a first state of said select signal, said first and second XOR arrangements influence said output signal;
- and
- in response to a second state of said select signal, a third input signal received by said XOR/SUMMER/MUX device output influences said output signal.
Dependencies are inferred from the claim text.