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US 6,642,766 B2Granted
Digital circuit, LSI including the same and method for removing noise
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorNorio Hatanaka
Life of this patent
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Abstract
A digital circuit, which avoids problems in LSIs including erroneous operation even when noise is superposed on a clock signal, is provided. A frequency divider divides the frequency of a first clock signal to generate a raw clock signal. A first flip-flop synchronizes the raw clock signal with a second clock signal. A second flip-flop synchronizes an output signal of the first flip-flop with the first clock signal and outputs the synchronized signal as a reproduced clock signal.
Claims13
A digital circuit comprising:
- a clock generator which receives a first clock signal and generates a raw clock signal synchronized with the first clock signal;
- a first circuit section which outputs the raw clock signal synchronously with a second clock signal;
- and
- a second circuit section which outputs, as a reproduced clock signal, the output signal from the first circuit section synchronously with the first clock signal.
1 more element
A method for removing noise, comprising the steps of:
- a) generating a raw clock signal synchronized with a first clock signal from the first clock signal;
- b) synchronizing the raw clock signal with a second clock signal;
- and
- c) synchronizing the signal obtained by the step b) with the first clock signal, thereby generating a reproduced clock signal.
1 more element
A digital circuit comprising:
- a clock generator which receives a first clock signal and generates a raw clock signal synchronized with the first clock signal;
- a first circuit section which outputs the raw clock signal synchronously with a second clock signal;
- and
- a second circuit section which outputs, as a reproduced clock signal, the output signal from the first circuit section synchronously with the first clock signal;
- a differentiator circuit section which receives said second clock signal as a clock signal and said raw clock signal as a data signal, said differentiator outputs a third clock signal;
- a first counter which operates synchronously with said first clock signal and which counts a number of pulses of said reproduced clock signal;
- and
- a second counter which operates synchronously with said second clock signal and which counts a number of pulses of said third clock signal.
5 more elements
Dependencies are inferred from the claim text.