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US 6,642,765 B2Granted
Transmission-gate based flip-flop
AssigneeIntel Corporation
InventorsDejan Markovic, James W. Tschanz, Vivek K. De
Life of this patent
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Abstract
Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.
Claims26
An apparatus comprising:
- flip-flop circuitry including;
- an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal,
- a clock terminal configured to provide a timing signal for reception of the input signal at the input and transmission of the output signal at the output,
- two on-path inverters connected serially between the input and output, the two on-path inverters being configured not to respond to the timing signal,
- two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signal,
- two transmission gate transistors respectively connected serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter, and
- a pair of additional transistors connected in parallel with one of the transmission gate transistors.
4 more elements
A method comprising:
- passing an input signal through two on-path inverters from an input to an output of a flip-flop;
- controlling the timing of passing of the input signal to the output using two feedback inverters that are connected respectively in parallel with the two on-path inverters and are responsive to a timing signal, the on-path inverters not being directly responsive to the timing signal;
- passing the input signal through transmission gate transistors that connect serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter;
- and
- sensing the input signal at a pair of additional transistors connected in parallel with one of the transmission gate transistors.
2 more elements
A flip-flop comprising:
- an input configured to receive an input signal;
- an output configured to deliver an output signal corresponding to the input signal;
- a clock terminal configured to provide a timing signal for reception of the input signal at the input and transmission of the output signal at the output;
- two on-path inverters connected serially between the input and output, the two on-path inverters being configured not to respond to the timing signal;
- two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signal;
- transmission gate transistors connected serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter;
- and
- a pair of two additional transistors connected in parallel with one of the transmission gate transistors.
5 more elements
An apparatus comprising:
- a flip-flop including:
- an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal,
- two on-path inverters connected serially between the input and output,
- two feedback inverters respectively connected in parallel with the two on-path inverters,
- two transmission gate transistors respectively connected serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter, and
- a pair of additional transistors connected in parallel with one of the transmission gate transistors.
3 more elements
A method comprising:
- passing an input signal through two on-path inverters from an input to an output of a flip-flop;
- controlling the timing of passing of the input signal to the output using two feedback inverters that are connected respectively in parallel with the two on-path inverters;
- passing the input signal through transmission gate transistors that connect serially between the input and the first on-path inverter and between the first on-path inverter and the second on-path inverter,
- sensing the input signal at a pair of additional transistors connected in parallel with one of the transmission gate transistors.
1 more element
Dependencies are inferred from the claim text.