Long setup flip-flop for improved synchronization capabilities

A device for resolving metastability comprising:

• at least one master latch, wherein the at least one master latch receives a data signal and resolves a metastability condition of the data signal to generate a stable data signal;
• and
• a slave latch, wherein the slave latch receives the stable data signal resolved by the at least one master latch and displays the stable data signal;
• wherein:
• the metastability condition is resolved by extending a setup time before the data signal is received at the slave latch;
• the at least one master latch resolves the metastability condition of the data signal on a first clock phase and the slave latch receives and displays the stable data signal on a second clock phase;
• the first clock phase is maximized to allow the master latch to perform the resolution;
• and
• the first clock phase initiates on a falling edge of a clock pulse and the second clock phase initiates on a rising edge of the clock pulse.

A device for resolving metastability comprising:

• at least one master latch, wherein the at least one master latch receives a data signal and resolves a metastability condition of the data signal to generate a stable data signal;
• and
• a slave latch, wherein the slave latch receives the stable data signal resolved by the at least one master latch and displays the stable data signal;
• wherein the metastability condition is resolved by extending a setup time before the data signal is received at the slave latch;
• and
• wherein the slave latch is associated with a first metastability time resolution constant and the master latch being associated with a second metastability time resolution constant, the second metastability time resolution constant being less than the first metastability time resolution constant.

A device for resolving metastability comprising:

• at least one master latch, wherein the at least one master latch receives a data signal and resolves a metastability condition of the data signal to generate a stable data signal;
• and
• a slave latch, wherein the slave latch receives the stable data signal resolved by the at least one master latch and displays the stable data signal;
• wherein the metastability condition is resolved by extending a setup time before the data signal is received at the slave latch, the at least one master latch is a sense amp latch, and the sense amp latch includes a sense amplifier circuit and a plurality of cross-coupled CMOS inverters.

A device for resolving metastability comprising:

• at least one master latch, wherein the at least one master latch receives a data signal and resolves a metastability condition of the data signal to generate a stable data signal;
• and
• a slave latch, wherein the slave latch receives the stable data signal resolved by the at least one master latch and displays the stable data signal;
• wherein the metastability condition is resolved by extending a setup time before the data signal is received at the slave latch, the at least one master latch is a sense amp latch, and the slave latch is a jam latch.

A device for resolving metastability comprising:

• at least one master latch, wherein the at least one master latch receives a data signal and resolves a metastability condition of the data signal to generate a stable data signal;
• and
• a slave latch, wherein the slave latch receives the stable data signal resolved by the at least one master latch and displays the stable data signal;
• wherein the metastability condition is resolved by extending a setup time before the data signal is received at the slave latch, the at least one master latch is a sense amp latch, and the slave latch is a tri-stable latch.

A method for resolving metastability comprising:

• receiving a data signal having a metastable condition;
• resolving the metastable condition of the received data signal in at least one master latch to produce a stable data signal;
• receiving the stable data signal in a slave latch;
• and
• displaying the stable data signal;
• wherein the slave latch receives a complementary clock signal with respect to the at least one master latch, and the metastable condition is resolved by extending a setup time before the data signal is received at the slave latch.

A method for resolving metastability comprising:

• receiving a data signal having a metastable condition;
• resolving the metastable condition of the received data signal in at least one master latch to produce a stable data signal;
• receiving the stable data signal in a slave latch;
• displaying the stable data signal;
• and
• controlling the at least one master latch and the slave latch via a clock signal;
• wherein:
• the metastable condition is resolved by extending a setup time before the data signal is received at the slave latch;
• the metastable condition of the received data signal is resolved during a first phase of the clock signal and the stable data signal is displayed on a second phase of the clock signal;
• the first phase is maximized;
• and
• the first phase initiates on a falling edge of a clock pulse of the clock signal and the second phase initiates on a rising edge of the clock pulse.

A method for resolving metastability comprising:

• receiving a data signal having a metastable condition;
• resolving the metastable condition of the received data signal in at least one master latch to produce a stable data signal;
• receiving the stable data signal in a slave latch;
• and displaying the stable data signal;
• wherein:
• the metastable condition is resolved by extending a setup time before the data signal is received at the slave latch;
• the at least one master latch is a sense amp latch;
• and
• the sense amp latch includes a sense amplifier circuit and a plurality of cross-coupled CMOS inverters.

A method for resolving metastability comprising:

• receiving a data signal having a metastable condition;
• resolving the metastable condition of the received data signal in at least one master latch to produce a stable data signal;
• receiving the stable data signal in a slave latch;
• and
• displaying the stable data signal;
• wherein:
• the metastable condition is resolved by extending a setup time before the data signal is received at the slave latch;
• the at least one master latch is a sense amp latch;
• and
• the slave latch is a jam latch.

A method for resolving metastability comprising:

• receiving a data signal having a metastable condition;
• resolving the metastable condition of the received data signal in at least one master latch to produce a stable data signal;
• receiving the stable data signal in a slave latch;
• and
• displaying the stable data signal;
• wherein:
• the metastable condition is resolved by extending a setup time before the data signal is received at the slave latch;
• the at least one master latch is a sense amp latch;
• and
• the slave latch is a tri-stable latch.