Method and apparatus to ensure DLL locking at minimum delay

A method of operating a delay locked loop (DLL) circuit, the method comprising:

• generating one or more output signals from a phase detector, the one or more output signals indicative of a phase relationship between a reference clock signal and an output clock signal;
• establishing a first state in a flip-flop responsive to a reset of the DLL circuit;
• controlling a counter independent of the one or more output signals from the phase detector in response to the first state;
• and
• clocking the flip-flop with a signal derived from at least one of the one or more output signals of the phase detector, the flip-flop changing to a second state responsive to the signal, and wherein the counter control circuit is configured to terminate said controlling the counter responsive to detecting said second state.

A carrier medium comprising one or more databases representing:

• a delay line configured to delay the transitions of a reference clock signal;
• a counter coupled to the delay line, wherein the counter is coupled to provide a count to the delay line, wherein the amount of delay provided by the delay line is determined by the count;
• a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal;
• and
• the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit comprises a flip-flop, and wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to establish a first state in the flip-flop in which the counter control circuit is configured to control operation of the counter independent of the one or more output signals of the phase detector, and wherein the flip-flop is clocked by a signal derived from at least one of the one or more output signals of the phase detector, the flip-flop changing to a second state responsive to the signal, and wherein the counter control circuit is configured, responsive to the second state, to terminate the control that is independent of the one or more output signals from the phase detector.