Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell
AssigneeEtron Technology, Inc.
InventorLi-Chin Tien
Life of this patent
Estimating the term…
Abstract
A particular wide band interface circuit provides an interface between a very fast slope clock signal input and a very slow slope voltage controlled delay cell of a delay lock loop. The invention generates the internal clock signal to track the slope of each delay stage, whether it is a higher frequency for which the slope of the delay stage is faster or a lower frequency for which the slope of the delay stage is slower. The integrated circuit includes a voltage bias portion, an analog clock input portion, circuit devices for interfacing with clock frequency inputs over all the available frequency range, and an output portion for producing clock signals. The invention applies to the multiple delay stages of a delay lock loop.
Claims17
A method of implementing a delay lock loop comprising:
- providing a phase detector having first inputs coupled with external clock signals and second inputs coupled with the outputs of a delay cell circuitry;
- providing a charge pump having inputs coupled with the outputs of the phase detector;
- providing a reference generator having an input operably coupled with the output of the charge pump;
- providing a voltage control delay line circuit having first inputs coupled with the outputs of the reference generator and second inputs coupled with the external clock signals;
- and
- providing said delay cell circuitry having first inputs coupled with the outputs of the voltage control delay line circuit and second inputs coupled with the outputs of the reference generator.
A clock buffered interface circuit comprising:
- a voltage controlled delay line cell having a differential clock input, having a p-channel bias input, having an n-channel bias input, and generating a differential clock output, wherein said differential clock output has a modified slope of said differential clock input based on said p-channel and n-channel bias inputs;
- and
- a delay cell having a delay cell differential clock input, having a p-channel bias delay cell input, having an n-channel bias delay cell input, and generating a differential clock delay cell output, wherein said differential clock delay cell output is a delayed version of said differential clock delay cell input based on said p-channel and n-channel bias delay cell inputs, wherein said differential clock delay cell input is coupled to said voltage controlled delay line cell differential clock output, and wherein said delay cell further comprises:
- a first n-channel transistor with gate coupled to a first polarity of said delay cell differential clock
- input and drain coupled to a first polarity of said delay cell differential clock output;
- a second n-channel transistor with gate coupled to a second polarity of said delay cell differential clock input and drain coupled to a second polarity of said delay cell differential clock output;
- a third n-channel transistor with gate coupled to said n-channel bias input, source coupled to ground, and drain coupled to sources of said first and second n-channel transistors;
- a first p-channel transistor with gate coupled to said p-channel bias input, drain coupled to said first polarity of said delay cell differential clock output, and source coupled to a power supply;
- and
- a second p-channel transistor with gate coupled to said p-channel bias input, drain coupled to said second polarity of said delay cell differential clock output, and source coupled to said power supply.
A delay lock loop circuit having an input coupled to a differential input clock signal and generating an output differential clock signal wherein said delay lock loop circuit comprises:
- a phase detector having a first input coupled to said delay lock loop differential input clock signal, having a second input, and generating an output;
- a charge pump having an input coupled to said phase detector output and generating an output;
- a reference generator having an input coupled to said charge pump output, generating a p-channel bias, and generating an n-channel bias;
- and
- a clock buffered interface circuit comprising:
- a voltage controlled delay line cell having a differential clock input coupled to said delay lock loop differential input clock signal, having a p-channel bias input coupled to said reference generator p-channel bias, having an n-channel bias input coupled to said reference generator n-channel bias, and generating a differential clock output, wherein said differential clock output has a modified slope of said differential clock input based on said p-channel and n-channel bias inputs;
- and
- a delay cell having a delay cell differential clock input, p-channel bias delay cell input, n-channel bias delay cell input, and generating a delay cell differential clock output, wherein said delay cell differential clock output is a delayed version of said delay cell differential clock input based on said p-channel and n-channel bias delay cell inputs, wherein said delay cell differential clock input is coupled to said voltage controlled delay line cell differential clock output, and wherein said delay cell differential clock output is coupled to said phase detector second input.
Dependencies are inferred from the claim text.