Apparatus and method for a digital delay locked loop

A circuit for selectively delaying a reference clock signal, the circuit comprising:

• a phase splitter for receiving a reference clock signal and outputting an in-phase reference signal and a complementary reference signal, where the complementary reference signal is complementary to the in-phase reference signal;
• a first delay line having an input for receiving the in-phase reference signal and a set of output taps for outputting the in-phase reference signal with successively increasing delay;
• a first multiplexor (MUX) having a plurality of inputs, each one of the plurality of inputs being coupled to a corresponding one of the set of output taps of the first delay line, the first MUX having a control input for receiving a first control signal for selecting one of the plurality of inputs for coupling to an output of the first MUX;
• a second delay line having an input for receiving the complementary reference signal and a set of output taps for outputting the complementary reference signal with successively increasing delay;
• a second MUX having a plurality of inputs, each one of the plurality of inputs being coupled to a corresponding one of the set of output taps of the second delay line, the second MUX having a control input for receiving the first control signal for selecting one of the plurality of inputs for coupling to an output of the second MUX;
• a first latch having a set input coupled to the output of the first MUX, a reset input coupled to the output of the second MUX, and an output for producing an output clock signal;
• a phase detector having a first input for receiving a feedback clock signal corresponding to the output clock signal, a second input for receiving an input clock signal, where the phase detector is configured to output a difference signal at an output of the phase detector that indicates a phase relationship between the feedback clock signal and the input clock signal;
• and
• a controller having an input for receiving the difference signal and an output for generating the first control signal, where the controller is configured to adjust the control signal responsive to the difference signal so as to align the feedback clock signal and the input clock signal.

A method for recovering a clock signal from an input clock signal, comprising the steps of:

• converting a reference clock signal into an in-phase reference signal and a complementary reference signal;
• delaying the in-phase reference signal and the complementary reference signal;
• generating an output clock signal from the delayed in-phase reference signal and the complementary reference signal;
• comparing a feedback signal representing the output clock signal to the input clock signal to generate a first control signal;
• and
• adjusting a length of delay for at least one of the in-phase reference signal and the complementary reference signal based upon the control signal.

A method for recovering a clock signal from an input clock signal, the method comprising the steps of:

• converting a reference clock signal into an in-phase reference signal and a complementary reference signal;
• successively delaying the in-phase reference clock signal to produce a series of delayed in-phase reference clock signals;
• successively delaying the complementary reference clock signal to produce a series of delayed complementary reference clock signals;
• selecting a first one of the series of delayed in-phase reference clock signals and a first one of the series of delayed complementary reference clock signals responsive to a first control signal, where the first one of the series of delayed complementary reference clock signals corresponds to the first one of the series of delayed in-phase reference clock signals;
• generating an output clock signal by producing a rising edge in the output clock signal responsive to a rising edge in the first one of the series of delayed in-phase reference clock signals and producing a falling edge in the output clock signal responsive to a rising edge in the first one of the series of delayed complementary reference clock signals;
• receiving the input clock signal;
• comparing the input clock signal to a feedback clock signal related to the output clock signal to produce a difference signal;
• and
• generating the first control signal responsive to the difference signal in order to bring the feedback clock signal into phase with the input clock signal.

An apparatus for recovering an input clock signal, the apparatus comprising:

• means for generating a reference clock signal having a correct duty cycle;
• means for converting the reference clock signal into an in-phase reference signal and a complementary reference signal;
• means for successively delaying the in-phase reference clock signal to produce a series of delayed in-phase reference clock signals;
• means for successively delaying the complementary reference clock signal to produce a series of delayed complementary reference clock signals;
• means for selecting a first one of the series of delayed in-phase reference clock signals and a first one of the series of delayed complementary reference clock signals responsive to a first control signal, where the first one of the series of delayed complementary reference clock signals corresponds to the first one of the series of delayed in-phase reference clock signals;
• means for generating an output clock signal by producing a rising edge in the output clock signal responsive to a rising edge in the first one of the series of delayed in-phase reference clock signals and producing a falling edge in the output clock signal responsive to a rising edge in the first one of the series of delayed complementary reference clock signals;
• means for receiving the input clock signal;
• means for comparing the input clock signal to a feedback clock signal related to the output clock signal to produce a difference signal;
• and
• means for generating the first control signal responsive to the difference signal in order to bring the feedback clock signal into phase with the input clock signal.