Frequency multiplier design
AssigneeSun Microsystems, Inc.
InventorsGin Yee, Sudhakar Bobba, Lynn Ooi, Pradeep Trivedi
Life of this patent
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Abstract
A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is provided. The frequency multiplier design uses circuitry dependent on the output clock signal to reset the flip-flop after some delay but before the second transition of the input clock signal, wherein the resetting of the flip-flop causes the flip-flop to output the second edge on the output clock signal.
Claims15
An integrated circuit, comprising:
- a flip-flop with a clock input operatively connected to a first clock signal wherein the flip-flop is arranged to generate a second clock signal;
- a pulse generator with an input operatively connected to the second clock signal;
- and
- a voltage controlled delay element with an input operatively connected to an output of the pulse generator and an output operatively connected to a reset input of the flip-flop,
- wherein the flip-flop is a dual-edge triggered resettable flip-flop.
An integrated circuit, comprising:
- flip-flop means for inputting a first transition of a first clock signal and outputting a first type of edge on a second clock signal upon receipt of the first transition;
- and
- means for resetting the flip-flop means before the flip-flop means inputs a second transition of the first clock signal, wherein the flip-flop means outputs a second type of edge on the second clock signal dependent on the means for resetting the flip-flop means.
A method for multiplying a frequency of a first clock signal, comprising:
- generating a first type of edge on a second clock signal dependent on a first transition of the first clock signal;
- generating a pulse dependent on the first type of edge;
- delaying the pulse;
- and
- generating a second type of edge on the second clock signal dependent on the pulse, wherein generating the second type of edge occurs before receipt of a second transition of the first clock signal.
Dependencies are inferred from the claim text.