Clock signal generator employing a DDS circuit
AssigneeSiemens Aktiengesellschaft
InventorsDieter Dobramysl, Ludwig Hofmann, Frank Lillie
Life of this patent
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Abstract
A clock signal generator having a DDS circuit which adds up a frequency word with a particular frequency and generates an output pulse when an overflow occurs. To reduce jitter, a parameter value corresponding to the ideal overflow time of the DDS circuit is determined and an output pulse generating circuit determines, in dependence on the parameter value and using a further, higher frequency, a corrected time for the output pulse and outputs the output pulse at this corrected time.
Claims14
A clock signal generator comprising:
- a DDS circuit for adding up a frequency word according to a first frequency, generating a first output pulse, and generating an overflow signal when the DDS circuit overflows;
- a circuit arrangement for determining a parameter value which corresponds to an ideal overflow time of the DDS circuit in dependence on the first output pulse and the overflow signal;
- and
- an output pulse generating circuit for determining a corrected time for a second output pulse in dependence on the parameter value, determined by the circuit arrangement, using a second frequency which is higher than the first frequency, and for outputting the second output pulse at the corrected time for generating a clock signal.
A clock signal generator configured to generate a clock signal, the clock signal generator comprising:
- a DDS circuit configured to add up a frequency word according to a first frequency, generate a first output pulse, and generate an overflow signal when the DDS circuit overflows;
- a circuit arrangement configured to determine a parameter value that corresponds to an ideal overflow time of the DDS circuit based on the first output pulse and the overflow signal;
- and
- an output pulse generating circuit configured to determine a corrected time for a second output pulse dependent on the parameter value using a second frequency, which is higher than the first frequency, and output the second output pulse at the corrected time to generate the clock signal.
Dependencies are inferred from the claim text.