Latching sense amplifier with tri-state output
AssigneeLSI Logic Corporation
InventorsSifang Wu, Steven M. Peterson, Mai T. MacLennan
Life of this patent
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Abstract
A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.
Claims16
A tri-state sense amplifier comprising:
- an enable input;
- a latch comprising first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input;
- first and second voltage supply terminals, wherein the latch is biased between the first and second voltage supply terminals;
- an enable circuit coupled in series between the latch and the second voltage supply terminal and having an enable control terminal coupled to the enable input;
- and
- an output driver comprising a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.
A tri-state sense amplifier comprising:
- an enable input;
- a latch comprising first and second complementary inputs and first and second complementary latch outputs;
- first and second voltage supply terminals, wherein the latch is biased between the first and second voltage supply terminals;
- an enable circuit coupled in series between the latch and the second voltage supply terminal and having an enable control terminal coupled to the enable input;
- an output driver comprising a data output, a pull-up transistor coupled to the data output and having a control terminal driven by the first latch output, and a pull-down transistor coupled to the data output and having a control terminal driven by the second latch output;
- first logic gate coupled between the first latch output and the control terminal of the pull-up transistor, and gates the first latch output with the enable input;
- and
- second logic gate coupled between the second latch output and the control terminal of the pull-down transistor, and gates the second latch output with the enable input.
A tri-state sense amplifier comprising:
- an enable input;
- a latch comprising first and second complementary inputs and first and second complementary latch outputs;
- first and second voltage supply terminals, wherein the latch is biased between the first and second voltage supply terminals;
- enable means coupled in series between the latch and at least one of the first and second voltage supply terminals for selectively enabling the latch as a function of the enable input;
- logic means for gating the first and second latch outputs with the enable input to produce first and second complementary gated outputs, respectively;
- and
- output driver means for producing a data output based on the first and second complementary gated outputs, wherein the data output has either a logic high state, a logic low state or a high impedance state.
Dependencies are inferred from the claim text.