Frequency detector for a phase locked loop system

An apparatus for detecting a difference in frequencies between a first input signal and a second input signal, comprising:

• a clear logic circuit that is arranged to activate a clear signal when a first intermediate signal and a second intermediate signal correspond to a first logic level, and arranged to deactivate the clear signal when at least one of the first intermediate signal and the second intermediate signal corresponds to a second logic level, wherein the second logic level is an inverse of the first logic level;
• a first flip-flop circuit that is arranged to set the first intermediate signal to the first logic level in response to the first input signal when the clear signal is deactivated, and arranged to reset the first intermediate signal to the second logic level when the clear signal is activated;
• a second flip-flop circuit that is arranged to set the second intermediate signal to the first logic level in response to the second input signal when the clear signal is deactivated, and arranged to reset the second intermediate signal to the second logic level when the clear signal is activated;
• a third flip-flop circuit that is arranged to activate an up signal in response to the first input signal when the first intermediate signal corresponds to the first logic level, such that the up signal is activated when the first input signal pulses twice before the clear signal is activated;
• a fourth flip-flop circuit that is arranged to activate a down signal in response to the second input signal when the second intermediate signal corresponds to the first logic level, such that the down signal is activated when the second input signal pulses twice before the clear signal is activated, wherein the up and down signals are related to the difference in frequencies between the first input signal and the second input signal;
• and
• a first delay circuit that is arranged to provide the first intermediate signal to the third flip-flop circuit after a predetermined delay, and a second delay circuit that is arranged to provide the second intermediate signal to the fourth flip-flop circuit after another predetermined delay, such that the third and fourth flip-flop circuits have stable input signals when the first and second input signals transition.

An apparatus for detecting a difference between a frequency that is associated with a clock signal and a frequency that is associated with a reference clock signal, comprising:

• a first means for detecting a transition in the reference clock signal and providing a first intermediate signal that has a first logic level;
• a second means for detecting a transition in the clock signal and providing a second intermediate signal that has a first logic level;
• a means for resetting arranged to provide a clear signal when the first and second intermediate signals correspond to the first logic level, such that the clear signal sets the first and second intermediate signals to a second logic level when the clear signal is asserted, wherein the second logic level is an inverse of the first logic level;
• a first means for delaying that is arranged to provide a first delayed signal in response to the first intermediate signal, wherein the first delayed signal is related to the first intermediate signal according to a delay factor;
• a third means for receiving the first delayed signal and detecting a transition in the reference clock signal to provide an up signal when the reference clock pulses at least twice without asserting the clear signal;
• a fourth means for receiving the second intermediate signal and detecting a transition in the clock signal to provide a down signal when the reference clock pulses at least twice without asserting the clear signal.

An apparatus for detecting a difference between a frequency that is associated with a clock signal and a frequency that is associated with a reference clock signal, comprising:

• a first means for detecting a transition in the reference clock signal and providing a first intermediate signal that has a first logic level;
• a second means for detecting a transition in the clock signal and providing a second intermediate signal that has a first logic level;
• a means for resetting arranged to provide a clear signal when the first and second intermediate signals correspond to the first logic level, such that the clear signal sets the first and second intermediate signals to a second logic level when the clear signal is asserted, wherein the second logic level is an inverse of the first logic level;
• a second means for delaying that is arranged to provide a second delayed signal in response to the second intermediate signal, wherein the second delayed signal is related to the second intermediate signal according to a delay factor;
• a third means for receiving the first intermediate signal and detecting a transition in the reference clock signal to provide an up signal when the reference clock pulses at least twice without asserting the clear signal;
• and
• a fourth means for receiving the second delayed signal and detecting a transition in the clock signal to provide a down signal when the reference clock pulses at least twice without asserting the clear signal.

A phase-locked-loop system, comprising:

• a voltage controlled oscillator that is arranged to provide a VCO clock signal, wherein the VCO clock signal has a corresponding frequency of f2 that is adjusted in response to a VCO input signal;
• a phase detector circuit that provides a first up signal and a first down signal in response to a reference clock signal and the VCO clock signal, wherein the reference clock signal has a corresponding frequency of f1, wherein the phase detector circuit comprises:
• a first NAND logic circuit that is arranged to provide the first up signal in response to the reference clock signal and an inverse of the VCO clock signal;
• a second NAND logic circuit that is arranged to provide the first down signal in response to the reference clock signal an the VCO clock signal;
• and
• an inverter circuit that is arranged to provide the inverse of the VCO clock signal in response to the VCO clock signal;
• a first charge-pump circuit that is arranged to provide a first current in response to the first up signal and the first down signal;
• a frequency detector circuit that provides a second up signal and a second down signal in response to the reference clock signal and the VCO clock signal, wherein an average logic level of the second up signal corresponds to zero when f2≧f1, the average logic level of the second up signal corresponds to (1−(f2/f1)) when f1>f2, an average logic level of the second down signal corresponds to zero when f1≧f2, and an average logic level of the second down signal corresponds to (1−(f1/f2)) when f2>f1;
• a second charge-pump circuit that is arranged to provide a second current in response to the second up signal and the second down signal such that the second current has an average value that is related to the average logic levels of the second up signal and the second down signal;
• and
• a capacitor circuit that is arranged to provide the VCO input signal in response to the first current and the second current, wherein the frequency detector circuit is arranged to acquire a frequency lock between the reference clock signal and the VCO clock signal, and the phase detector circuit is arranged to adjust the phase between the reference clock signal and the VCO clock signal.