System for rapid configuration of a programmable logic device
AssigneeSTMicroelectronics S.r.l.
InventorAnkur Bal
Life of this patent
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Abstract
A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.
Claims30
A system for configuring at least one programmable logic device comprising a configuration memory, the system comprising:
- first means for selecting a logically continuous array of bits from the configuration memory;
- second means for selecting at least one of the bits from the selected logically continuous array of bits which requires toggling;
- and
- third means for changing the at least one bit which requires toggling.
A system for configuring at least one programmable logic device comprising a configuration memory, the system comprising:
- a write control shift register for selecting a logically continuous a ray of bits from the configuration memory;
- a decoder for selecting at least one of the bits from the selected logically continuous array of bits which requires toggling;
- and
- a transistor for changing the at least one bit which requires toggling.
A method for configuring at least one programmable logic device comprising a configuration memory, the method comprising:
- selecting a logically continuous array of bits from the configuration memory;
- selecting at least one of the bits from the selected logically continuous array of bits which requires toggling;
- and
- changing the at least one bit which requires toggling.
Dependencies are inferred from the claim text.