Method and apparatus for controlling output impedance

A method for controlling output impedance from a I/O circuit, the method comprising:

• providing a first plurality of resistive elements connected in parallel between a first reference node and an output node arid a second plurality of resistive elements connected in parallel between the second reference node and a reference node, wherein each of the first plurality of resistive elements and each of the second plurality of resistive elements includes a control terminal coupled to a control circuit, wherein the output node is coupled to a core circuit and a signal line;
• activating one or more of the first plurality of resistive elements during a logic high transmission from the core circuit onto the signal line, wherein the first plurality includes first, second, and third resistive elements, wherein each of the first, second, and third resistive elements is of a substantially different resistance with respect to each other, wherein said activating one or more of the first plurality is performed by the control circuit;
• and
• activating one or more of the second plurality of resistive elements during a logic low transmission from the core circuit onto the signal line, wherein the second plurality includes fourth, fifth, and sixth resistive elements, wherein each of the fourth, fifth, and sixth resistive elements is of a substantially different resistance with respect to each other, wherein said activating one or more of the second plurality is performed by the control circuit.

An system comprising:

• a core circuit;
• and
• and I/O circuit configured to transmit signals originating in the core circuit, the I/O circuit comprising:
• a first plurality of resistive elements connected in parallel between a first reference node and an output node and a second plurality of resistive elements connected in parallel between the output node and a second reference node, wherein each of the first plurality of resistive elements and each of the second plurality of resistive elements includes a control terminal, and wherein the output node is coupled to a core circuit and a signal line;
• and
• a control circuit coupled to the control terminal of each of the first plurality of resistive elements and each of the second plurality of resistive elements, wherein the control circuit is configured to activate one or more of the first plurality of resistive elements during a logic high transmission from the core circuit onto the signal line, and wherein the control circuit is configured to activate one or more of the second plurality of resistive elements during a logic low transmission from the core circuit onto the signal line;
• wherein the first plurality includes first, second, and third resistive elements, wherein each of the first, second, and third resistive elements is of a substantially different resistance with respect to each other;
• and
• wherein the second plurality includes fourth, fifth, and sixth resistive elements, wherein each of the fourth, fifth, and sixth resistive elements is of a substantially different resistance with respect to each other.

An input/output (I/O) circuit comprising:

• a first plurality of transistors and a second plurality of transistors, wherein each of the first plurality of transistors is in parallel between a first reference node and an output node, and wherein each of the second plurality of transistors is connected in parallel between the output node and a second reference node, wherein the output node is configured to convey a logic transmission received from a core circuit;
• a control circuit coupled to a control terminal of each of the first plurality of transistors and each of the second plurality of transistors, wherein the control circuit is configured to activate one or more of the first plurality of transistors during a logic high transmission received from the core circuit and one or more of the second plurality of transistors during a logic low transmission received from the core circuit;
• wherein each of the first plurality of transistors and has a substantially different drain-source resistance with respect to other transistors of the first plurality;
• and
• wherein each of the second plurality of transistors has a substantially different drain-source resistance with respect to other transistors of the second plurality.