Chip carrier device and method for the production of a chip carrier device with an electrical test
AssigneesPac Tech—Packaging Technologies GmbH, Smart Pac GmbH Technology Services
InventorsHartmut Rohde, Gerhild Wendland
Life of this patent
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Abstract
A chip carrier arrangement (10) for an encased chip arrangement has a chip carrier (11), whose one chip contact side (24) exhibits a conductor path structure (12) with a terminal face (17) extending to an outer contact side (25) of the chip carrier and allocated to at least one chip (18) with a through connection (14). The chip carrier (11) has additional through connections (14) connected with the conductor path structure (12), which are used for contacting with test connections (32) of a test board (29, 30).
Claims14
A chip carrier arrangement for manufacturing a chip module for an encased chip arrangement with a chip carrier, the arrangement comprising:
- a chip contact side on the chip carrier with a conductor path structure including through connections extending to an outer contact side of the chip carrier, said through connections being allocated to terminal faces of at least one chip, and said through connections being used to form component contacts on the outer contact side of the chip carrier;
- additional through connections associated with said chip carrier, said additional through connections being connected with said conductor path structure, said additional through connections forming test contacts on the outer contact side of the chip carrier allocated to a chip and arranged along one peripheral edge of the chip.
An arrangement comprising:
- a carrier substrate having a first and second side, said carrier substrate defining a plurality of component and test electrical through holes forming electrical paths from said first side to said second side;
- a plurality of conductor paths arranged on said first side of said carrier substrate, said plurality of conductor paths forming a plurality of chip receiving sites, said plurality of conductor paths being arranged at said plurality of chip receiving sites to contact terminal faces of chips received at a respective said chip receiving site, said plurality of conductor paths extending from said chip receiving site to said test electrical through holes;
- a plurality of test contacts arranged on said second side of said carrier substrate and formed as part of said test electrical through holes, said plurality of test contacts being arranged along a peripheral edge of said carrier substrate;
- a plurality of component contacts arranged on said second side of said carrier substrate and formed as part of said component electrical through holes, said component electrical through holes being allocated to the terminal faces of the chips received at said chip receiving sites.
Dependencies are inferred from the claim text.