High-speed peaking circuit for characteristic impedance control
AssigneeTeradyne, Inc.
InventorsCosmin Iorga, Alan B. Hussey, Gary Evans, Lucian Maria
Life of this patent
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Abstract
A high-speed tester channel architecture is disclosed for delivering and receiving signals to and from a device-under-test. The tester channel architecture includes drive/compare circuitry having respective driver and comparator transmission line paths and backmatch resistor circuitry to establish a backmatch condition. Peaking circuitry is disposed in each of the driver and comparator transmission line paths. The peaking circuitry includes a capacitive branch and an inductive branch operative to preserve the backmatch condition.
Claims6
A high-speed tester channel architecture for delivering and receiving signals to and from a device-under-test, said tester channel architecture including:
- drive/compare circuitry having respective driver and comparator transmission line paths defining a backmatch condition;
- peaking circuitry disposed in each of said driver and comparator transmission line paths, said peaking circuitry including
- capacitive branch circuitry, and
- inductive branch circuitry, said capacitive and inductive branch circuitry operative to cooperate to preserve said backmatch condition.
A high-speed tester channel architecture including:
- a drive path having
- a first transmission line with a first characteristic impedance;
- a driver having an output including a backmatch resistance for establishing a backmatched condition with respect to the transmission line;
- and
- peaking circuitry coupled to the first transmission line, the peaking circuitry comprising a continuous spectrum filter including an RC circuit and an RL circuit, both the RC circuit and the RL circuit having substantially the same time time constant T and configured to preserve the transmission line characteristic impedance.
Dependencies are inferred from the claim text.