Voltage mode boost converter using a period-fixed amplitude-modulated pulse control signal
AssigneeFaraday Technology Corp.
InventorJia Jio Huang
Life of this patent
Estimating the term…
Abstract
A voltage mode boost converter includes a control signal generating circuit, a step-up circuit, and a feedback circuit. The control signal generating circuit generates a step-up control pulse signal with a fixed period and a modulated amplitude. The step-up circuit adjusts an output voltage signal of the step-up circuit according to the step-up control pulse signal generated by the control signal generating circuit. The feedback circuit is electrically connected between the control signal generating circuit and the step-up circuit for generating a feedback voltage signal in accordance with the output voltage signal of the step-up circuit.
Claims9
A voltage mode boost converter comprising:
- a control signal generating circuit for generating a step-up control pulse signal with a fixed period and a modulated amplitude in response to a first reference voltage signal, a second reference voltage signal, a timing pulse signal, and a feedback voltage signal, the control signal generating circuit including:
- an amplitude control circuit having:
- a first comparator with a first input terminal, a second input terminal for receiving the first reference voltage signal, and a first output terminal for outputting an amplitude control signal, the first comparator being switched between a standby mode and an active mode in accordance with the timing pulse signal;
- a first resistor electrically connected to the first input terminal such that the feedback voltage signal is input into the first terminal through the first resistor;
- and
- a second resistor electrically connected between the first input terminal and the first output terminal, and
- a modulation circuit having:
- a second comparator with a third input terminal for receiving the feedback voltage signal, a fourth input terminal for receiving the second reference voltage signal, and a second output terminal;
- a logic gate with a fifth input terminal electrically connected to the second output terminal, a sixth input terminal for receiving the timing pulse signal, and a third output terminal;
- a PMOS transistor with a gate electrode electrically connected to the third output terminal, a source electrode for receiving the amplitude control signal, and a drain electrode;
- and
- an NMOS transistor with a gate electrode electrically connected to the third output terminal, a drain electrode electrically connected to the drain electrode of the PMOS transistor for outputting the step-up control pulse signal with the fixed period and the modulated amplitude, and a source electrode electrically connected to a ground;
- a step-up circuit electrically connected to the control signal generating circuit for adjusting an output voltage signal of the step-up circuit in accordance with the step-up control pulse signal with the fixed period and the modulated amplitude;
- and
- a feedback circuit electrically connected between the control signal generating circuit and the step-up circuit for generating the feedback voltage signal in accordance with the output voltage signal of the step-up circuit and for inputting the feedback voltage signal to the control signal generating circuit.
Dependencies are inferred from the claim text.