Semiconductor chip having bond pads and multi-chip package

A semiconductor chip having one or more peripheral bond pads, the semiconductor chip comprising:

• a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other;
• a bond pad-wiring pattern formed on the semiconductor substrate;
• a passivation layer formed on the semiconductor substrate and on the bond pad-wiring pattern;
• a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern;
• and
• an insulating layer formed over the pad-rearrangement pattern, the insulating layer having an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad, the bond pad disposed over at least a part of the cell region,
• wherein the pad-wiring pattern is formed substantially in a center region of the semiconductor substrate.

A semiconductor chip having a bond pad, the chip comprising:

• a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other;
• a bond pad-wiring pattern formed on at least a portion of the peripheral circuit region electrically connected thereto;
• a passivation layer formed on the semiconductor substrate and on the bond pad-wiring pattern;
• a first interlayer dielectric layer formed over the semiconductor substrate including the bond pad-wiring pattern;
• a second interlayer dielectric layer formed over the first interlayer dielectric layer;
• a first opening extending through the passivation layer and the first and second interlayer dielectric layers to expose a portion of the bond pad-wiring pattern,
• a second opening extending through the second interlayer dielectric layer to expose a portion of the first interlayer dielectric layer;
• a pad-rearrangement pattern formed over the second interlayer dielectric layer and within the first opening and electrically connected to the bond pad-wiring pattern and within the second opening;
• and
• an insulating layer formed over the pad-rearrangement pattern, the insulating layer having an opening therein that exposes a portion of the pad-rearrangement pattern formed within the second opening to form the pad over at least a part of the cell region,
• wherein the bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate.

A semiconductor chip comprising:

• a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other;
• a bond pad-wiring pattern formed on the semiconductor substrate;
• and
• a pad-rearrangement pattern electrically connected to the bond pad-wiring pattern, the pad-rearrangement pattern including a bond pad disposed over at least a part of the cell region,
• wherein a portion of the pad-rearrangement pattern extends substantially from a center region of the semiconductor substrate toward an edge of the semiconductor substrate.