Semiconductor memory device and manufacturing method thereof

A memory device including a substrate and an array of memory cells on the substrate, each of the cells comprising:

• a memory node overlying the substrate for capacitatively storing a level of electrical charge;
• an insulating layer between the memory node and the substrate, electrically isolating the memory node from the substrate so that no significant leakage current flows between the memory node and the substrate;
• and
• a controllable conduction device comprising a charge carrier path coupled to the memory node for changing the level of charge held by the memory node, and a gate for switching the conductivity of the path between conductive and non-conductive conditions to change the level of charge stored by the memory node, wherein the controllable conduction device overlies the memory node.

A method of fabricating a memory device on a substrate comprising:

• forming a memory node overlying the substrate for capacitatively storing a level of electrical charge;
• providing an insulating layer between the memory node and the substrate, configured so that in use of the memory device no significant leakage current flows between the memory node and the substrate;
• and
• fabricating a controllable conduction device comprising a charge carrier path coupled to the memory node for changing the level of charge held by the memory node, and a gate for switching the conductivity of the path between conductive and non-conductive conditions to change the level of charge stored by the memory node, the controllable conduction device being fabricated in a configuration that overlies the memory node.

A memory device comprising:

• a substrate;
• a memory node overlying the substrate for capacitatively storing a level of electrical charge;
• an insulating layer between the memory node and the substrate, electrically isolating the memory node from the substrate so that no significant leakage current flows between the memory node and the substrate;
• and
• a vertical transistor overlying the memory node, the vertical transistor having an upper contact and a vertical charge carrier path coupled between the upper contact and the memory node for changing the level of charge held by the memory node, and a gate electrically insulated from the vertical charge carrier path for switching the conductivity there of between conductive and non-conductive conditions to change the level of charge stored by the memory node.

A memory device comprising:

• a substrate,
• an electrically insulating layer on the substrate,
• a first vertical transistor structure comprising source, barrier and drain regions formed in an overlying configuration upstanding from the insulating layer, and a side gate formed on the upstanding configuration, the barrier region being formed of material which provides an internal electrostatic barrier potential of a relatively high barrier height to inhibit charge carrier flow along the path between the source and drain regions, the barrier height being selectively lowerable in response to an external bias being applied to the gate so that charge carriers can pass along the path between the source and drain regions,
• a memory node coupled to the first vertical transistor structure, and
• a second transistor coupled to the memory node,
• said first and second transistors overlying one another.

A memory device including a substrate and an array of memory cells on the substrate, each of the cells comprising:

• a first vertical transistor structure comprising source, barrier and drain regions formed in an overlying configuration upstanding from the insulating layer, and a side gate formed on the upstanding configuration, the barrier region being formed of material which provides an internal electrostatic barrier potential of a relatively high barrier height to inhibit charge carrier flow along the path between the source and drain regions, the barrier height being selectively lowerable in response to an external bias being applied to the gate so that charge carriers can pass along the path between the source and drain regions,
• a memory node coupled to the first vertical transistor structure, and
• a second transistor coupled to the memory node,
• said first and second transistors overlying one another.

A method of fabricating a memory device comprising:

• providing a substrate,
• forming an electrically insulating layer on the substrate,
• fabricating a first vertical transistor structure comprising source, barrier and drain regions in an overlying configuration upstanding from the insulating layer, and a side gate on the upstanding configuration, the barrier region being formed of material which provides an internal electrostatic barrier potential of a relatively high barrier height to inhibit charge carrier flow along the path between the source and drain regions, the barrier height being selectively lowerable in response to an external bias being applied to the gate so that charge carriers can pass along the path between the source and drain regions,
• providing a memory node coupled to the first vertical transistor structure, and
• fabricating a second transistor coupled to the memory node such that said first and second transistors overlie one another.