Use of high-K dielectric material in modified ONO structure for semiconductor devices

A non-volatile memory cell comprising:

• a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween;
• b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric material layer;
• and
• c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate, a top dielectric material layer adjacent to the control gate, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprises a mid-K or high-K dielectric material, and at least one of the bottom dielectric material layer or the top dielectric material layer comprises a composite dielectric material including elements of a high-K dielectric material and at least one additional dielectric material,
• wherein each mid-K or high-K dielectric material independently comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), barium titanate (BaTiO3), cerium oxide (CeO2), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), lead zirconate (PbZrO3), tungsten oxide (WO3), yttrium oxide (Y2O3), bismuth silicon oxide (Bi4Si2O12), barium strontium titanate (BST) (Ba1-xSrxTiO3), PMN (PbMgxNb1-xO3), PZT (PbZrxTi1-xO3), PZN (PbZnxNb1-xO3), and PST (PbScxTa1-xO3).

A non-volatile memory cell comprising:

• a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween;
• b) a charge storage layer comprising a modified ONO structure, the modified ONO structure having a bottom dielectric material layer adjacent the channel region, a top dielectric material layer, and a center charge storage layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprises a mid-K or high-K dielectric material, wherein each mid-K or high-K dielectric material independently comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), barium titanate (BaTiO3), cerium oxide (CeO2), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), lead titanate (PbTiO3), strontium titanate (SrTiO3), lead zirconate (PbZrO3), tungsten oxide (WO3), yttrium oxide (Y2O3), bismuth silicon oxide (Bi4Si2O12), barium strontium titanate (BST) (Ba1-xSrxTiO3), PMN (PbMgxNb1-xO3), PZT (PbZrxTi1-xO3), PZN (PbZnxNb1-xO3), and PST (PbScxTa1-xO3);
• and
• c) a gate capacitively coupled to the channel region through the charge storage layer,
• and wherein at least one of the bottom dielectric material layer or the top dielectric material layer comprises a composite dielectric material including elements of the high-K dielectric material and at least one additional dielectric material.