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US 6,642,563 B2Granted
Semiconductor memory including ferroelectric gate capacitor structure, and method of fabricating the same
AssigneeKabushiki Kaisha Toshiba
InventorHiroyuki Kanaya
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Abstract
A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a hole at a position corresponding to a channel region. In the channel length direction, the hole extends across the channel region. A ferroelectric gate capacitor structure is formed in the hole. The ferroelectric gate capacitor structure includes a dielectric film, ferroelectric film, and upper electrode formed in this order from the substrate side.
Claims34
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- a semiconductor substrate;
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region;
- an upper electrode embedded in said first recess;
- and
- a conductive contact plug electrically connected to the upper electrode, said contact plug having a central portion disposed in contact with an upper surface of said upper electrode, and an extending portion extending beyond opposite ends of said upper electrode in said channel length direction, said extending portion being disposed in contact with an upper surface of said capacitor insulating film around said upper surface of said upper electrode.
4 more elements
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- a semiconductor substrate;
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer includinq a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region;
- an upper electrode embedded in said first recess;
- a wiring layer formed above said capacitor insulating film and said upper electrode;
- and
- a hydrogen barrier layer interposed between said capacitor insulating film and said wiring layer, and between said upper electrode and said wiring layer.
5 more elements
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- a semiconductor substrate;
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film formed to cover a bottom surface of said hole and contact side surfaces of said hole, said capacitor insulating film being disposed in contact with said channel region of said substrate;
- and
- an upper electrode formed to cover said capacitor insulating film in said hole and contact said side surfaces of said hole,
- wherein said capacitor insulating film and said upper electrode have different lengths in said channel length direction, and first and second portions of said hole on the same level as said capacitor insulating film and said upper electrode have different lengths in said channel length direction.
4 more elements
A method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- forming a source layer and a drain layer in a surface of a semiconductor substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in said surface of said substrate interposed therebetween;
- forming, on said surface of said substrate, an insulating interlayer extending from said source layer to said drain layer and including a hole at a position corresponding to said channel region, said hole extending across said channel region in said channel length direction;
- sequentially stacking a dielectric film, a capacitor insulating film comprising a ferroelectric film, and an upper electrode film on said insulating interlayer to cover bottom and side surfaces of said hole;
- removing portions of said dielectric film, said capacitor insulating film, and said upper electrode film on said insulating interlayer by planarization;
- forming a sacrificial structure at a position on said substrate corresponding to said channel region;
- forming said source layer and said drain layer by implanting impurity ions into said surface of said substrate by using said sacrificial structure as a mask;
- forming said insulating interlayer on said substrate to surround said sacrificial structure;
- and
- forming said hole in said insulating interlayer by removing said sacrificial structure by etching.
6 more elements
A method of fabricating a semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- forming a source layer and a drain layer in a surface of a semiconductor substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in said surface of said substrate interposed therebetween;
- forming, on or above the surface of said substrate, a first insulating interlayer extending from said source layer to said drain layer and including a first recess at a position corresponding to said channel region;
- stacking a capacitor insulating film comprising a ferroelectric film on said first insulating interlayer to cover bottom and side surfaces of said first recess;
- removing a portion of said capacitor insulating film on said first insulating interlayer by planarization, thereby leaving said capacitor insulating film in said first recess;
- forming, on said first insulating interlayer and said capacitor insulating film, a second insulating interlayer including a second recess at a position corresponding to said channel region and exposing said capacitor insulating film, said first and second recesses having different lengths in said channel length direction;
- depositing an upper electrode film on said second insulating interlayer to cover bottom and side surfaces of said second recess;
- removing a portion of said upper electrode film on said second insulating interlayer by planarization;
- forming a sacrificial structure at a position on said substrate corresponding to said channel region;
- forming said source layer and said drain layer by implanting impurity ions into said surface of said substrate by using said sacrificial structure as a mask;
- forming a lowermost insulating interlayer on said substrate to surround said sacrificial structure;
- and
- forming a lowermost hole in said lowermost insulating interlayer by removing said sacrificial structure by etching.
9 more elements
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- a semiconductor substrate;
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region;
- an upper electrode embedded in said first recess, said upper electrode having an upper surface, which is flat and leveled with an upper surface of said capacitor insulating film and an upper surface of said insulating interlayer therearound;
- and
- a conductive contact plug disposed in contact with said upper surface of said upper electrode.
4 more elements
A semiconductor memory including a ferroelectric gate capacitor structure, comprising:
- a semiconductor substrate;
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film formed to cover a bottom surface of said hole and contact side surfaces of said hole;
- and
- an upper electrode formed to cover said capacitor insulating film in said hole and contact said side surfaces of said hole;
- a dielectric film formed between said substrate and said capacitor insulating film to cover the bottom surface of said hole, said dielectric film being disposed in contact with said channel region of said substrate,
- wherein said capacitor insulating film and said upper electrode have different lengths in said channel length direction, and first and second portions of said hole on the same level as said capacitor insulating film and said upper electrode have different lengths in said channel length direction.
5 more elements
A semiconductor memory comprising a first transistor including a ferroelectric gate capacitor structure, and a second transistor functioning as a switching transistor, both formed on a semiconductor substrate,
- wherein said first transistor comprises:
- a source layer and a drain layer formed in a surface of said substrate, said source layer and said drain layer opposing each other in a channel length direction with a channel region in the surface of said substrate interposed therebetween;
- an insulating interlayer formed on said surface of said substrate to extend from said source layer to said drain layer, said insulating interlayer including a hole at a position corresponding to said channel region, and said hole extending across said channel region in said channel length direction;
- a capacitor insulating film comprising a ferroelectric film and formed to cover bottom and side surfaces of said hole, said capacitor insulating film including a first recess at a position corresponding to said channel region;
- and
- an upper electrode embedded in said first recess, and
- wherein said second transistor comprises a gate electrode having a length substantially the same as that of the first recess, in said channel length direction.
4 more elements
Dependencies are inferred from the claim text.