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US 6,642,557 B2Granted
Isolated junction structure for a MOSFET
AssigneeIntel Corporation
InventorChunlin Liang
Life of this patent
Estimating the term…
Abstract
A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.
Claims17
A MOSFET structure, comprising:
- a semiconductor substrate having pedestals integrally formed on a surface of the semiconductor substrate, the pedestals having a top portion and a stem portion;
- a gate insulator layer superadjacent the top portion of the pedestal;
- a gate electrode overlying the gate insulator layer;
- and
- a junction isolation region adjacent the pedestals, wherein the junction isolation region is filled with a gas and at least one other dielectric material.
2 more elements
A MOSFET structure, comprising:
- a semiconductor substrate having pedestals integrally formed in the semiconductor substrate, wherein the pedestals have a top portion and a stem portion, wherein the top portion has doped source and drain regions;
- a junction isolation region formed in the substrate to isolate the source and drain regions from the substrate, wherein the junction isolation region reduces junction capacitance of the MOSFET structure, wherein the junction isolation region is filled with at least two dielectric materials, wherein one of the at least two dielectric materials is a gas;
- a gate insulating layer superadjacent the top portion of the pedestal;
- and
- a gate electrode overlying the gate insulator layer.
2 more elements
Dependencies are inferred from the claim text.