Hybrid silicon on insulator/bulk strained silicon technology
AssigneeAdvanced Micro Devices, Inc.
InventorsQi Xiang, Akif Sultan
Life of this patent
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Abstract
Silicon on insulator technology and strained silicon technology provide semiconductor devices with high performance capabilities. Shallow trench isolation technology provides smaller devices with increased reliability. Bulk silicon technology provides devices requiring deep ion implant capabilities and/or a high degree of thermal management. A semiconductor device including silicon on insulator regions, strained silicon layer, shallow trench isolation structures, and bulk silicon regions is provided on a single semiconductor substrate.
Claims13
A semiconductor device comprising:
- a semiconductor substrate comprising a base layer,
- a silicon germanium (SiGe) layer formed on the base layer;
- a silicon layer formed on the SiGe layer, wherein the SiGe layer contains a first T region in which an isolation region is formed therein, and a second region;
- a plurality of field effect transistors (FET) including a first FET formed over the isolation region in the first region;
- and
- a second FET formed in the second region, wherein the isolation region comprises undercut portions in contact with the silicon layer and the undercut portions extend alongside and directly below the silicon layer.
A semiconductor device comprising:
- a semiconductor substrate comprising a base layer,
- a silicon germanium (SiGe) layer formed on the base layer;
- a silicon layer formed on the SiGe layer, wherein the SiGe layer contains a first region in which an isolation region is formed therein, and a second region;
- a plurality of field effect transistors (FET) including a first FET formed over the isolation region in the first region;
- and
- a second FET formed in the second region, wherein the first FET and the second FET comprise source and drain regions, and the source and drain regions of said first FET are confined to the silicon layer.
A semiconductor device comprising:
- a semiconductor substrate comprising a base layer,
- a SiGe layer formed on the base layer,
- a silicon layer formed on the SiGe layer,
- an isolation region extending through the silicon layer into the SiGe layer, and
- a transistor formed on a portion of the substrate overlying the isolation region, wherein the isolation region comprises undercut portions in contact with the silicon layer and the undercut portions extend alongside and directly below the silicon layer.
Dependencies are inferred from the claim text.