Assembly and method for improved scanning electron microscope analysis of semiconductor devices
AssigneeTexas Instruments Incorporated
InventorsFred Y. Clark, James D. Krouse, Ping Jiang, Robyn R. Carlson
Life of this patent
Estimating the term…
Abstract
An assembly and method for improved scanning electron microscope analysis of semiconductor devices include a structure including a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV, and at least part of the surface of the structure coated with a material composed of Iridium, wherein the coating is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
Claims21
An assembly for improved scanning electron microscope analysis of semiconductor devices, comprising:
- a structure comprising a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV;
- and
- a coating on at least part of the surface of the structure, the coating comprised of Iridium and of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
A method for improved scanning electron microscope analysis of semiconductor devices, comprising:
- providing a structure comprising a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV;
- and
- coating at least part of the surface of the structure with a material comprising Iridium;
- wherein the coating is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
A method for improved scanning electron microscope analysis of semiconductor devices, comprising:
- providing an assembly, comprising:
- a structure comprising a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV, and
- a coating on at least part of the surface of the structure, the coating comprised of Iridium and of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV;
- and
- examining the structure with a scanning electron microscope having a beam energy of at least 1.5 KeV.
An assembly for improved scanning electron microscope analysis of semiconductor devices, comprising:
- a structure comprising a first layer and a second layer, the second layer comprising a material having at least a low dielectric constant;
- and
- a coating of Iridium on at least part of the surface of the structure, the coating of sufficient thickness to reduce shrinkage of the second layer to approximately one-tenth of one percent when the structure is examined with a scanning electron microscope with a beam energy of at least 1.5 KeV.
Dependencies are inferred from the claim text.