Method of making a low fabrication cost, high performance, high reliability chip scale package
AssigneeMegic Corporation
InventorsJin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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AssigneeMegic Corporation
InventorsJin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
Estimating the term…
A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.
A method for forming a re-routed metal bump on a semiconductor surface, comprising the steps of:
A method for forming a metal bump on a semiconductor surface, comprising the steps of:
Dependencies are inferred from the claim text.