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US 6,642,133 B2Granted
Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
AssigneeIntel Corporation
InventorsBrian Roberds, Doulgas W. Barlage
Life of this patent
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Abstract
The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
Claims30
A method, comprising:
- forming a gate stack including a first spacer on a semiconductive layer, the semiconductive layer overlying an insulator layer and the insulator layer overlying a substrate;
- by a gate stack self-aligned etch, first etching through the semiconductive layer and through a portion of the insulator layer;
- forming a second spacer at the gate stack, the second spacer formed to the etched insulator layer so that the second spacer extends beneath the semiconductive layer;
- second etching through the insulator layer disposed beneath the semiconductive layer to form an undercut beneath the second spacer;
- and
- forming a contact at the undercut beneath the semiconductive layer, the contact to intercept and drain electromagnetic energy from the semiconductive layer.
3 more elements
A method, comprising:
- on a semiconductive layer of a substrate, forming a gate stack including a spacer, the semiconductive layer overlying an insulator layer and the insulator layer overlying the substrate;
- by a gate stack self-aligned etch, forming a recess through the semiconductive layer and through the insulator layer below the semiconductive layer;
- forming an inside contact beneath the semiconductive layer in the recess that is self-aligned along one side thereof with the first spacer, the inside contact to intercept and drain electromagnetic energy from the semiconductive layer;
- and
- forming an outside contact in the recess that is spaced apart and opposite the inside contact.
2 more elements
A method, comprising:
- forming a gate stack including a first spacer on a semiconductive layer, the semiconductive layer overlying an insulator layer and the insulator layer overlying a silicon substrate;
- performing a first etch, self-aligned with the gate stack, entirely through the semiconductive layer and into a portion of the insulator layer, the insulator layer etched to a small distance beneath a bottom extremity of the semiconductive layer;
- forming a second spacer at the gate stack, the second spacer formed along the entire side length of, and below, the first spacer so that a bottom end of the second spacer bottoms out on the etched insulator layer;
- performing a second etch that penetrates through the insulator layer to a top surface of the underlying substrate to form an undercut beneath the second spacer, the undercut extending from the bottom end of the second spacer to the top surface of the substrate;
- depositing a conductive film over the gate stack, over the first and second spacers, over the top surface of the substrate, and within the undercut;
- and
- performing a third etch in alignment with an outside edge of the second spacer, the third etch removing the conductive film from over the gate stack, from over the first and second spacers and from over the substrate, the second spacer protecting the conductive film from being etched within the undercut thus forming a vertically oriented conductor at the undercut beneath the semiconductive layer, the vertically oriented conductor having a bottom end that connects to the surface of the substrate and a top end that terminates said small distance from the bottom extremity of the semiconductive layer so as not to connect with the semiconductive layer, the vertically oriented conductor to intercept and drain electromagnetic energy away from the semiconductive layer.
4 more elements
Dependencies are inferred from the claim text.