Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-chul Oh, Gyo-young Jin
Life of this patent
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Abstract
An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.
Claims22
A method of forming an integrated circuit comprising:
- forming a first trench in one of a core region and a peripheral region of an integrated circuit substrate;
- forming a second trench in a cell region of the integrated circuit that is adjacent to the core and peripheral regions, the second trench being narrower than the first trench;
- forming an insulator layer in the first and second trenches;
- forming a liner layer on the insulator layer in the first and second trenches;
- forming a mask on the second trench that exposes the first trench;
- and
- removing the liner layer from the first trench and avoiding removing the liner layer from the second trench to reduce a stress between the integrated circuit substrate and the insulator layer in the second trench.
A method of manufacturing a semiconductor device having an STI structure, comprising:
- providing a semiconductor substrate defined as a cell region in which memory devices are formed and core and peripheral regions in which a PMOS transistor is formed;
- forming a blocking pattern on the semiconductor substrate to expose a predetermined region for defining the cell, core and peripheral regions of the semiconductor substrate and providing isolation between devices in respective regions;
- forming a plurality of trenches by etching exposed regions of the semiconductor substrate to a predetermined depth using the blocking pattern as a mask;
- forming a side wall oxide layer on inner surfaces of the plurality of trenches;
- forming a plurality of relief liners in the plurality of trenches on the side wall oxide layers therein;
- removing the relief liner from a selected one of the plurality of trenches between PMOS transistors;
- depositing a dielectric material to completely fill the plurality of the trenches;
- and
- forming an STI layer by chemically and mechanically polishing the dielectric material, the relief liner, and the blocking pattern.
A method of forming an integrated circuit in an integrated circuit device comprising:
- forming a liner layer on side walls of first isolation trenches located in a cell region of an integrated circuit substrate to provide stress relief between a dielectric in the first isolation trenches and the substrate;
- and
- avoiding forming the liner layer on side walls of second isolation trenches located in a peripheral region of the substrate.
Dependencies are inferred from the claim text.