Double-gate FET with planarized surfaces and self-aligned silicides
AssigneeInternational Business Machines Corporation
InventorsGuy M. Cohen, Hon-Sum P. Wong
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Abstract
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).
Claims22
A method of producing a double-gate metal oxide semiconductor field effect transistor comprising:
- forming a film stack including a first sacrificial layer, a channel layer above said first sacrificial layer, and a second sacrificial layer above said channel layer;
- bonding said film stack to a water to form a laminated structure;
- removing said first sacrificial layer and said second sacrificial layer;
- and
- depositing gate conductors around at least two sides of said channel layer.
A method of producing a double-gate metal oxide semiconductor field effect transistor comprising:
- forming a first sacrificial layer on a first surface of a channel layer;
- forming a second sacrificial layer on a second surface of said channel layer;
- forming additional laminated layers on said first sacrificial layer and said second sacrificial layer to form a laminated structure;
- removing said first sacrificial layer and said second sacrificial layer;
- depositing a conductor to form double gate conductors around at least two sides of said channel layer;
- forming source and drain regions adjacent said channel layer, and
- simultaneously siliciding said gate conductors and said source and drain regions.
A method of producing a double-gate metal oxide semiconductor field effect transistor comprising:
- forming a laminated structure including a first sacrificial layer, a channel layer above said first sacrificial layer, a second sacrificial layer above said channel layer, an insulator layer above said second sacrificial layer, and a third sacrificial layer above said insulator layer;
- and
- removing said first sacrificial layer, said second sacrificial layer, and said third sacrificial layer to leave said channel layer as a first suspended bridge and said insulator layer as a second suspended bridge above said first suspended bridge;
- and
- depositing gate conductors around at least two sides of said channel layer.
Dependencies are inferred from the claim text.