Non-oxidizing spacer densification method for manufacturing semiconductor devices
AssigneeZilog, Inc.
InventorsBrett D. Lowe, John A. Smythe, Timothy K. Carns
Life of this patent
Estimating the term…
Abstract
Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.
Claims14
A method of forming a semiconductor structure on a substrate, comprising:
- forming a memory oxide on a semiconductor substrate;
- forming a doped floating gate polysilicon layer on said memory oxide;
- forming an inter-poly oxide layer on said doped floating gate polysilicon layer;
- forming a polycide structure comprising at least one polysilicon layer and at least one metal silicide layer;
- forming a spacer oxide on said polycide structure, said spacer oxide being formed to at least partially surround said polycide structure;
- and
- densifying said spacer oxide in a non-oxidizing ambient to form said semiconductor structure;
- wherein at least a portion of said polycide structure is not encapsulated during said densifying of said spacer oxide;
- wherein said polycide structure comprises a part of a MOSFET semiconductor device;
- wherein said polycide comprises tungsten silicide;
- wherein said non-oxidizing ambient comprises nitrogen gas, and wherein said method further comprises densifying said spacer oxide by exposing said spacer oxide to an oxide-densifying temperature for a period of time effective to densify said spacer oxide in said nitrogen gas;
- and
- wherein said method further comprises forming said polycide structure on said inter-poly oxide layer, said inter-poly oxide layer and said polycide structure together forming said non-volatile memory structure.
A method of forming a non-volatile memory stack structure and a non-memory control gate stack structure of an integrated semiconductor device on a silicon substrate, said method comprising:
- forming a dielectric isolation region on said silicon substrate, said dielectric isolation region being formed between an active non-volatile memory mesa area and an active non-memory mesa area of said silicon substrate;
- forming a memory cell oxide layer on said silicon substrate over said active non-volatile memory mesa area;
- forming a doped floating gate polysilicon layer on said memory cell oxide layer over said active non-volatile memory mesa area;
- forming an inter-poly oxide layer on said doped floating gate polysilicon layer over said active non-volatile memory mesa area;
- forming a thin gate oxide layer on said silicon substrate over said active non-memory mesa area;
- forming a doped control gate polysilicon layer on said thin gate oxide of said active non-memory mesa area and on said inter-poly oxide layer of said active non-volatile memory mesa area;
- forming a refractory metal silicide layer on said doped control gate polysilicon layer over said active non-volatile memory mesa area so as to form a non-volatile memory stack structure over said active non-volatile memory mesa area;
- forming heavily doped non-volatile memory source/drain regions of said non-volatile memory stack structure in said silicon substrate over said active non-volatile memory mesa area;
- forming a refractory metal silicide layer on said doped control gate polysilicon layer over said active non-memory mesa area so as to form a non-memory control gate stack structure over said active non-memory mesa area;
- forming lightly doped non-memory source/drain regions of said non-memory control gate stack structure in said silicon substrate over said active non-memory mesa area;
- forming a spacer oxide side layer on each of said non-volatile memory stack and said non-memory control gate stack structures;
- densifying said spacer oxide side layers in a non-oxidizing ambient;
- and
- forming heavily doped non-memory source/drain regions of said non-memory control gate stack structure in said silicon substrate over said lightly doped non-memory source/drain regions.
A method of forming a MOSFET non-volatile memory semiconductor structure on a substrate, comprising:
- forming a memory oxide on a semiconductor substrate;
- forming a doped floating gate polysilicon layer on said memory oxide;
- forming an inter-poly oxide layer on said doped floating gate polysilicon layer;
- forming a polycide structure on said inter-poly oxide layer, said polycide structure having at least one polysilicon layer and at least one metal silicide layer and comprising tungsten silicide, said inter-poly oxide layer and said polycide structure together forming said non-volatile memory structure of a MOSFET semiconductor device;
- forming a spacer oxide on said polycide structure, said spacer oxide being formed to at least partially surround said polycide structure;
- and
- densifying said spacer oxide in a non-oxidizing ambient comprising nitrogen gas to form said non-volatile memory semiconductor structure by exposing said spacer oxide to an oxide-densifying temperature for a period of time effective to densify said spacer oxide in said nitrogen gas.
Dependencies are inferred from the claim text.