Structure for capacitor-top-plate to bit-line-contact overlay margin

An array of memory cells on a dynamic random access memory (DRAM) device comprised of:

• a substrate having partially completed DRAM devices consisting of an array of device areas surrounded and electrically isolated by field oxide regions, each of said device areas having field effect transistors with gate electrodes and first and second source/drain areas;
• a first insulating layer having conducting first plug contacts to said first source/drain areas for capacitors, and having conducting second plug contacts to said second source/drain areas for bit-line contacts;
• a second insulating layer on said first insulating layer, and said second insulating layer having first openings aligned over and to said first plug contacts;
• capacitor bottom electrodes formed from a conformal first conducting layer in said first openings;
• said second insulating layer having recessed second openings from top surface of said second insulating layer between said capacitor bottom electrodes while leaving non-recessed portions of said second insulating layer over said second plug contacts;
• an interelectrode dielectric layer on said capacitor bottom electrodes;
• capacitor top plates composed of a second conducting layer that fills said first openings, said second conducting layer coplanar and self-aligned to said non-recessed portions of said second insulating layer over said second plug contacts;
• a third insulating layer over said top plates, and having third openings aligned over said second plug contacts, and said third openings extending through said second insulating layer to said second plug contacts, and said third openings filled with a third conducting layer for bit-line contacts;
• a patterned fourth conducting layer over said bit-line contacts for bit lines.